f69078b77f
Trying to reduce the diffs from D118333 for cases where it makes more sense to use an FP ABI. Reviewed By: asb, kito-cheng Differential Revision: https://reviews.llvm.org/D120447
119 lines
3.1 KiB
LLVM
119 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64d | FileCheck %s -check-prefix=RV64ID
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; This file exhaustively checks double<->i32 conversions. In general,
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; fcvt.l[u].d can be selected instead of fcvt.w[u].d because poison is
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; generated for an fpto[s|u]i conversion if the result doesn't fit in the
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; target type.
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define i32 @aext_fptosi(double %a) nounwind {
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; RV64ID-LABEL: aext_fptosi:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
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; RV64ID-NEXT: ret
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%1 = fptosi double %a to i32
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ret i32 %1
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}
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define signext i32 @sext_fptosi(double %a) nounwind {
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; RV64ID-LABEL: sext_fptosi:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
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; RV64ID-NEXT: ret
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%1 = fptosi double %a to i32
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ret i32 %1
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}
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define zeroext i32 @zext_fptosi(double %a) nounwind {
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; RV64ID-LABEL: zext_fptosi:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.w.d a0, fa0, rtz
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; RV64ID-NEXT: slli a0, a0, 32
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; RV64ID-NEXT: srli a0, a0, 32
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; RV64ID-NEXT: ret
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%1 = fptosi double %a to i32
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ret i32 %1
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}
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define i32 @aext_fptoui(double %a) nounwind {
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; RV64ID-LABEL: aext_fptoui:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
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; RV64ID-NEXT: ret
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%1 = fptoui double %a to i32
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ret i32 %1
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}
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define signext i32 @sext_fptoui(double %a) nounwind {
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; RV64ID-LABEL: sext_fptoui:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.wu.d a0, fa0, rtz
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; RV64ID-NEXT: ret
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%1 = fptoui double %a to i32
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ret i32 %1
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}
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define zeroext i32 @zext_fptoui(double %a) nounwind {
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; RV64ID-LABEL: zext_fptoui:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.lu.d a0, fa0, rtz
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; RV64ID-NEXT: ret
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%1 = fptoui double %a to i32
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ret i32 %1
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}
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define double @uitofp_aext_i32_to_f64(i32 %a) nounwind {
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; RV64ID-LABEL: uitofp_aext_i32_to_f64:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.d.wu fa0, a0
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; RV64ID-NEXT: ret
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%1 = uitofp i32 %a to double
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ret double %1
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}
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define double @uitofp_sext_i32_to_f64(i32 signext %a) nounwind {
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; RV64ID-LABEL: uitofp_sext_i32_to_f64:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.d.wu fa0, a0
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; RV64ID-NEXT: ret
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%1 = uitofp i32 %a to double
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ret double %1
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}
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define double @uitofp_zext_i32_to_f64(i32 zeroext %a) nounwind {
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; RV64ID-LABEL: uitofp_zext_i32_to_f64:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.d.wu fa0, a0
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; RV64ID-NEXT: ret
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%1 = uitofp i32 %a to double
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ret double %1
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}
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define double @sitofp_aext_i32_to_f64(i32 %a) nounwind {
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; RV64ID-LABEL: sitofp_aext_i32_to_f64:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.d.w fa0, a0
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; RV64ID-NEXT: ret
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%1 = sitofp i32 %a to double
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ret double %1
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}
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define double @sitofp_sext_i32_to_f64(i32 signext %a) nounwind {
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; RV64ID-LABEL: sitofp_sext_i32_to_f64:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.d.w fa0, a0
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; RV64ID-NEXT: ret
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%1 = sitofp i32 %a to double
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ret double %1
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}
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define double @sitofp_zext_i32_to_f64(i32 zeroext %a) nounwind {
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; RV64ID-LABEL: sitofp_zext_i32_to_f64:
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; RV64ID: # %bb.0:
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; RV64ID-NEXT: fcvt.d.w fa0, a0
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; RV64ID-NEXT: ret
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%1 = sitofp i32 %a to double
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ret double %1
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}
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