d9ba1a9c5c
We normally select these when the root node is a sext_inreg, but SimplifyDemandedBits can sometimes bypass the sext_inreg for some users. This can create situation where sext_inreg+add/sub/mul/shl is selected to a W instruction, and then the add/sub/mul/shl is separately selected to a non-W instruction with the same inputs. This patch tries to detect when it would still be ok to use a W instruction without the sext_inreg by checking the direct users. This can allow the W instruction to CSE with one created for a sext_inreg+add/sub/mul/shl. To minimize complexity and cost of checking, we make no attempt to determine if the CSE will happen and just always use a W instruction when we can. Differential Revision: https://reviews.llvm.org/D107658
27 lines
906 B
LLVM
27 lines
906 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck %s
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; This test has multiple opportunities for SimplifyDemandedBits after type
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; legalization. There are 2 opportunities on the chain feeding the LHS of the
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; shl. And one opportunity on the shift amount. We previously weren't managing
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; the DAGCombiner worklist correctly and failed to get the RHS.
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define i32 @foo(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulw a0, a0, a0
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; CHECK-NEXT: addiw a0, a0, 1
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; CHECK-NEXT: mulw a0, a0, a0
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; CHECK-NEXT: addw a0, a0, a2
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; CHECK-NEXT: addiw a0, a0, 1
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; CHECK-NEXT: sllw a0, a0, a1
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; CHECK-NEXT: ret
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%b = mul i32 %x, %x
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%c = add i32 %b, 1
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%d = mul i32 %c, %c
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%e = add i32 %d, %z
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%f = add i32 %e, 1
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%g = shl i32 %f, %y
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ret i32 %g
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}
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