b784719904
The goal is support tail and mask policy in RVV builtins. We focus on IR part first. If the passthru operand is undef, we use tail agnostic, otherwise use tail undisturbed. Add passthru operand for VSLIDE1UP_VL and VSLIDE1DOWN_VL to support i64 scalar in rv32. The masked VSLIDE1 would only emit mask undisturbed policy regardless of giving mask agnostic policy until InsertVSETVLI supports mask agnostic. Reviewed by: craig.topper, rogfer01 Differential Revision: https://reviews.llvm.org/D117989
65 lines
2.1 KiB
LLVM
65 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v -O2 < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IV
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define <vscale x 1 x i64> @access_fixed_object(i64 *%val) {
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; RV64IV-LABEL: access_fixed_object:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -528
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; RV64IV-NEXT: .cfi_def_cfa_offset 528
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; RV64IV-NEXT: addi a1, sp, 8
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; RV64IV-NEXT: vl1re64.v v8, (a1)
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; RV64IV-NEXT: ld a1, 520(sp)
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; RV64IV-NEXT: sd a1, 0(a0)
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; RV64IV-NEXT: addi sp, sp, 528
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; RV64IV-NEXT: ret
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%local = alloca i64
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%array = alloca [64 x i64]
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%vptr = bitcast [64 x i64]* %array to <vscale x 1 x i64>*
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%v = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vptr
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%len = load i64, i64* %local
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store i64 %len, i64* %val
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ret <vscale x 1 x i64> %v
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}
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declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
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<vscale x 1 x i64>,
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<vscale x 1 x i64>,
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<vscale x 1 x i64>,
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i64);
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define <vscale x 1 x i64> @access_fixed_and_vector_objects(i64 *%val) {
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; RV64IV-LABEL: access_fixed_and_vector_objects:
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; RV64IV: # %bb.0:
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; RV64IV-NEXT: addi sp, sp, -544
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; RV64IV-NEXT: .cfi_def_cfa_offset 544
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: sub sp, sp, a0
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; RV64IV-NEXT: addi a0, sp, 24
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; RV64IV-NEXT: vl1re64.v v8, (a0)
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; RV64IV-NEXT: ld a0, 536(sp)
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; RV64IV-NEXT: addi a1, sp, 544
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; RV64IV-NEXT: vl1re64.v v9, (a1)
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; RV64IV-NEXT: vsetvli zero, a0, e64, m1, ta, mu
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; RV64IV-NEXT: vadd.vv v8, v8, v9
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; RV64IV-NEXT: csrr a0, vlenb
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; RV64IV-NEXT: add sp, sp, a0
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; RV64IV-NEXT: addi sp, sp, 544
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; RV64IV-NEXT: ret
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%local = alloca i64
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%vector = alloca <vscale x 1 x i64>
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%array = alloca [64 x i64]
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%vptr = bitcast [64 x i64]* %array to <vscale x 1 x i64>*
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%v1 = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vptr
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%v2 = load <vscale x 1 x i64>, <vscale x 1 x i64>* %vector
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%len = load i64, i64* %local
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%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
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<vscale x 1 x i64> undef,
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<vscale x 1 x i64> %v1,
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<vscale x 1 x i64> %v2,
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i64 %len)
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ret <vscale x 1 x i64> %a
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}
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