9b0f227d7b
The mask being NoRegister prevented the existing aliases from matching since NoRegister isn't in the VMV0 register class. To workaround this I've added new aliases that look for zero_reg. I had to motify tablegen to generate matching code for zero_reg. And as a consequence, I had to change the EmitPriority for an ARM alias that used zero_reg that started printing. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D121496
66 lines
2.9 KiB
LLVM
66 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
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; These tests check that the scalable-vector version of this series of
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; instructions does not get into an infinite DAGCombine loop. This was
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; originally exposing an infinite loop between an 'and' of two truncates being promoted
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; to the larger value type, then that 'truncate' being split back up into an
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; 'and' of two truncates.
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; This didn't happen in the fixed-length test because a truncate of the
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; constant BUILD_VECTOR is folded into the BUILD_VECTOR itself. The truncate of
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; a constant SPLAT_VECTOR didn't follow suit.
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define <2 x i16> @fixedlen(<2 x i32> %x) {
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; RV32-LABEL: fixedlen:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; RV32-NEXT: vsrl.vi v8, v8, 16
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; RV32-NEXT: lui a0, 1048568
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; RV32-NEXT: vand.vx v8, v8, a0
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; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; RV32-NEXT: vncvt.x.x.w v8, v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: fixedlen:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; RV64-NEXT: vsrl.vi v8, v8, 16
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; RV64-NEXT: lui a0, 131071
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; RV64-NEXT: slli a0, a0, 3
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; RV64-NEXT: vand.vx v8, v8, a0
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; RV64-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; RV64-NEXT: vncvt.x.x.w v8, v8
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; RV64-NEXT: ret
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%v41 = insertelement <2 x i32> poison, i32 16, i32 0
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%v42 = shufflevector <2 x i32> %v41, <2 x i32> poison, <2 x i32> zeroinitializer
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%v43 = lshr <2 x i32> %x, %v42
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%v44 = trunc <2 x i32> %v43 to <2 x i16>
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%v45 = insertelement <2 x i32> poison, i32 -32768, i32 0
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%v46 = shufflevector <2 x i32> %v45, <2 x i32> poison, <2 x i32> zeroinitializer
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%v47 = trunc <2 x i32> %v46 to <2 x i16>
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%v48 = and <2 x i16> %v44, %v47
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ret <2 x i16> %v48
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}
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define <vscale x 2 x i16> @scalable(<vscale x 2 x i32> %x) {
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; CHECK-LABEL: scalable:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
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; CHECK-NEXT: vnsrl.wi v8, v8, 16
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; CHECK-NEXT: lui a0, 1048568
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: ret
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%v41 = insertelement <vscale x 2 x i32> poison, i32 16, i32 0
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%v42 = shufflevector <vscale x 2 x i32> %v41, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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%v43 = lshr <vscale x 2 x i32> %x, %v42
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%v44 = trunc <vscale x 2 x i32> %v43 to <vscale x 2 x i16>
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%v45 = insertelement <vscale x 2 x i32> poison, i32 -32768, i32 0
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%v46 = shufflevector <vscale x 2 x i32> %v45, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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%v47 = trunc <vscale x 2 x i32> %v46 to <vscale x 2 x i16>
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%v48 = and <vscale x 2 x i16> %v44, %v47
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ret <vscale x 2 x i16> %v48
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}
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