bbd2ecf9f0
Currently we allow half types in vectors if the scalar Zfh extension is enabled. This behavior is not inline with the vector spec. For f32 and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly control the availablity of floating point types in vectors. In order to make our compiler compliant, we either need to remove all support for half in vectors or we need an extension to control it. Draft spec here https://github.com/riscv/riscv-v-spec/pull/780 Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D121345
228 lines
9.1 KiB
LLVM
228 lines
9.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX8
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,LMULMAX1
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define void @fpext_v2f16_v2f32(<2 x half>* %x, <2 x float>* %y) {
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; CHECK-LABEL: fpext_v2f16_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vse32.v v9, (a1)
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; CHECK-NEXT: ret
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%a = load <2 x half>, <2 x half>* %x
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%d = fpext <2 x half> %a to <2 x float>
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store <2 x float> %d, <2 x float>* %y
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ret void
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}
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define void @fpext_v2f16_v2f64(<2 x half>* %x, <2 x double>* %y) {
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; CHECK-LABEL: fpext_v2f16_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; CHECK-NEXT: vfwcvt.f.f.v v8, v9
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; CHECK-NEXT: vse64.v v8, (a1)
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; CHECK-NEXT: ret
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%a = load <2 x half>, <2 x half>* %x
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%d = fpext <2 x half> %a to <2 x double>
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store <2 x double> %d, <2 x double>* %y
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ret void
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}
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define void @fpext_v8f16_v8f32(<8 x half>* %x, <8 x float>* %y) {
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; LMULMAX8-LABEL: fpext_v8f16_v8f32:
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; LMULMAX8: # %bb.0:
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; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
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; LMULMAX8-NEXT: vle16.v v8, (a0)
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; LMULMAX8-NEXT: vfwcvt.f.f.v v10, v8
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; LMULMAX8-NEXT: vse32.v v10, (a1)
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; LMULMAX8-NEXT: ret
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;
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; LMULMAX1-LABEL: fpext_v8f16_v8f32:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
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; LMULMAX1-NEXT: vle16.v v8, (a0)
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; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
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; LMULMAX1-NEXT: vslidedown.vi v9, v8, 4
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; LMULMAX1-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
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; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v9
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; LMULMAX1-NEXT: vfwcvt.f.f.v v9, v8
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; LMULMAX1-NEXT: addi a0, a1, 16
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; LMULMAX1-NEXT: vse32.v v10, (a0)
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; LMULMAX1-NEXT: vse32.v v9, (a1)
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; LMULMAX1-NEXT: ret
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%a = load <8 x half>, <8 x half>* %x
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%d = fpext <8 x half> %a to <8 x float>
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store <8 x float> %d, <8 x float>* %y
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ret void
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}
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define void @fpext_v8f16_v8f64(<8 x half>* %x, <8 x double>* %y) {
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; LMULMAX8-LABEL: fpext_v8f16_v8f64:
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; LMULMAX8: # %bb.0:
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; LMULMAX8-NEXT: vsetivli zero, 8, e16, m1, ta, mu
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; LMULMAX8-NEXT: vle16.v v8, (a0)
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; LMULMAX8-NEXT: vfwcvt.f.f.v v10, v8
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; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
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; LMULMAX8-NEXT: vfwcvt.f.f.v v12, v10
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; LMULMAX8-NEXT: vse64.v v12, (a1)
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; LMULMAX8-NEXT: ret
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;
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; LMULMAX1-LABEL: fpext_v8f16_v8f64:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
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; LMULMAX1-NEXT: vle16.v v8, (a0)
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; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
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; LMULMAX1-NEXT: vslidedown.vi v9, v8, 2
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; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
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; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v9
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; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vfwcvt.f.f.v v9, v10
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; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, ta, mu
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; LMULMAX1-NEXT: vslidedown.vi v10, v8, 4
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; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
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; LMULMAX1-NEXT: vslidedown.vi v11, v10, 2
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; LMULMAX1-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
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; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v11
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; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vfwcvt.f.f.v v11, v12
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; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v10
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; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vfwcvt.f.f.v v10, v12
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; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; LMULMAX1-NEXT: vfwcvt.f.f.v v12, v8
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; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vfwcvt.f.f.v v8, v12
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; LMULMAX1-NEXT: addi a0, a1, 32
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; LMULMAX1-NEXT: vse64.v v10, (a0)
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; LMULMAX1-NEXT: vse64.v v8, (a1)
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; LMULMAX1-NEXT: addi a0, a1, 48
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; LMULMAX1-NEXT: vse64.v v11, (a0)
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; LMULMAX1-NEXT: addi a0, a1, 16
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; LMULMAX1-NEXT: vse64.v v9, (a0)
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; LMULMAX1-NEXT: ret
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%a = load <8 x half>, <8 x half>* %x
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%d = fpext <8 x half> %a to <8 x double>
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store <8 x double> %d, <8 x double>* %y
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ret void
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}
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define void @fpround_v2f32_v2f16(<2 x float>* %x, <2 x half>* %y) {
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; CHECK-LABEL: fpround_v2f32_v2f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; CHECK-NEXT: vfncvt.f.f.w v9, v8
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; CHECK-NEXT: vse16.v v9, (a1)
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; CHECK-NEXT: ret
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%a = load <2 x float>, <2 x float>* %x
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%d = fptrunc <2 x float> %a to <2 x half>
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store <2 x half> %d, <2 x half>* %y
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ret void
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}
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define void @fpround_v2f64_v2f16(<2 x double>* %x, <2 x half>* %y) {
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; CHECK-LABEL: fpround_v2f64_v2f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; CHECK-NEXT: vle64.v v8, (a0)
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; CHECK-NEXT: vfncvt.rod.f.f.w v9, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; CHECK-NEXT: vfncvt.f.f.w v8, v9
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; CHECK-NEXT: vse16.v v8, (a1)
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; CHECK-NEXT: ret
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%a = load <2 x double>, <2 x double>* %x
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%d = fptrunc <2 x double> %a to <2 x half>
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store <2 x half> %d, <2 x half>* %y
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ret void
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}
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define void @fpround_v8f32_v8f16(<8 x float>* %x, <8 x half>* %y) {
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; LMULMAX8-LABEL: fpround_v8f32_v8f16:
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; LMULMAX8: # %bb.0:
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; LMULMAX8-NEXT: vsetivli zero, 8, e32, m2, ta, mu
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; LMULMAX8-NEXT: vle32.v v8, (a0)
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; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
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; LMULMAX8-NEXT: vfncvt.f.f.w v10, v8
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; LMULMAX8-NEXT: vse16.v v10, (a1)
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; LMULMAX8-NEXT: ret
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;
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; LMULMAX1-LABEL: fpround_v8f32_v8f16:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: addi a2, a0, 16
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; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
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; LMULMAX1-NEXT: vle32.v v8, (a0)
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; LMULMAX1-NEXT: vle32.v v9, (a2)
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; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
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; LMULMAX1-NEXT: vfncvt.f.f.w v10, v8
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; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
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; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
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; LMULMAX1-NEXT: vslideup.vi v10, v8, 4
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; LMULMAX1-NEXT: vse16.v v10, (a1)
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; LMULMAX1-NEXT: ret
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%a = load <8 x float>, <8 x float>* %x
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%d = fptrunc <8 x float> %a to <8 x half>
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store <8 x half> %d, <8 x half>* %y
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ret void
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}
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define void @fpround_v8f64_v8f16(<8 x double>* %x, <8 x half>* %y) {
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; LMULMAX8-LABEL: fpround_v8f64_v8f16:
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; LMULMAX8: # %bb.0:
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; LMULMAX8-NEXT: vsetivli zero, 8, e64, m4, ta, mu
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; LMULMAX8-NEXT: vle64.v v8, (a0)
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; LMULMAX8-NEXT: vsetvli zero, zero, e32, m2, ta, mu
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; LMULMAX8-NEXT: vfncvt.rod.f.f.w v12, v8
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; LMULMAX8-NEXT: vsetvli zero, zero, e16, m1, ta, mu
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; LMULMAX8-NEXT: vfncvt.f.f.w v8, v12
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; LMULMAX8-NEXT: vse16.v v8, (a1)
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; LMULMAX8-NEXT: ret
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;
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; LMULMAX1-LABEL: fpround_v8f64_v8f16:
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; LMULMAX1: # %bb.0:
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; LMULMAX1-NEXT: addi a2, a0, 48
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; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; LMULMAX1-NEXT: vle64.v v8, (a2)
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; LMULMAX1-NEXT: addi a2, a0, 32
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; LMULMAX1-NEXT: vle64.v v9, (a2)
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; LMULMAX1-NEXT: vle64.v v10, (a0)
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; LMULMAX1-NEXT: addi a0, a0, 16
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; LMULMAX1-NEXT: vle64.v v11, (a0)
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; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v10
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; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; LMULMAX1-NEXT: vfncvt.f.f.w v10, v12
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; LMULMAX1-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vfncvt.rod.f.f.w v12, v11
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; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; LMULMAX1-NEXT: vfncvt.f.f.w v11, v12
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; LMULMAX1-NEXT: vsetivli zero, 4, e16, m1, tu, mu
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; LMULMAX1-NEXT: vslideup.vi v10, v11, 2
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; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vfncvt.rod.f.f.w v11, v9
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; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; LMULMAX1-NEXT: vfncvt.f.f.w v9, v11
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; LMULMAX1-NEXT: vsetivli zero, 6, e16, m1, tu, mu
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; LMULMAX1-NEXT: vslideup.vi v10, v9, 4
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; LMULMAX1-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
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; LMULMAX1-NEXT: vfncvt.rod.f.f.w v9, v8
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; LMULMAX1-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
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; LMULMAX1-NEXT: vfncvt.f.f.w v8, v9
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; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, tu, mu
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; LMULMAX1-NEXT: vslideup.vi v10, v8, 6
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; LMULMAX1-NEXT: vse16.v v10, (a1)
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; LMULMAX1-NEXT: ret
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%a = load <8 x double>, <8 x double>* %x
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%d = fptrunc <8 x double> %a to <8 x half>
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store <8 x half> %d, <8 x half>* %y
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ret void
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}
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