bbd2ecf9f0
Currently we allow half types in vectors if the scalar Zfh extension is enabled. This behavior is not inline with the vector spec. For f32 and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly control the availablity of floating point types in vectors. In order to make our compiler compliant, we either need to remove all support for half in vectors or we need an extension to control it. Draft spec here https://github.com/riscv/riscv-v-spec/pull/780 Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D121345
50 lines
1.8 KiB
LLVM
50 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+experimental-zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+experimental-zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
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; Check that we are able to legalize scalable-vector loads that require widening.
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define <vscale x 3 x i8> @load_nxv3i8(<vscale x 3 x i8>* %ptr) {
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; CHECK-LABEL: load_nxv3i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: srli a1, a1, 3
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; CHECK-NEXT: slli a2, a1, 1
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; CHECK-NEXT: add a1, a2, a1
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: ret
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%v = load <vscale x 3 x i8>, <vscale x 3 x i8>* %ptr
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ret <vscale x 3 x i8> %v
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}
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define <vscale x 5 x half> @load_nxv5f16(<vscale x 5 x half>* %ptr) {
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; CHECK-LABEL: load_nxv5f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: srli a1, a1, 3
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; CHECK-NEXT: slli a2, a1, 2
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; CHECK-NEXT: add a1, a2, a1
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; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: ret
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%v = load <vscale x 5 x half>, <vscale x 5 x half>* %ptr
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ret <vscale x 5 x half> %v
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}
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define <vscale x 7 x half> @load_nxv7f16(<vscale x 7 x half>* %ptr, <vscale x 7 x half>* %out) {
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; CHECK-LABEL: load_nxv7f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a2, vlenb
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; CHECK-NEXT: srli a2, a2, 3
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; CHECK-NEXT: slli a3, a2, 3
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; CHECK-NEXT: sub a2, a3, a2
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; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vse16.v v8, (a1)
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; CHECK-NEXT: ret
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%v = load <vscale x 7 x half>, <vscale x 7 x half>* %ptr
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store <vscale x 7 x half> %v, <vscale x 7 x half>* %out
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ret <vscale x 7 x half> %v
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}
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