bbd2ecf9f0
Currently we allow half types in vectors if the scalar Zfh extension is enabled. This behavior is not inline with the vector spec. For f32 and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly control the availablity of floating point types in vectors. In order to make our compiler compliant, we either need to remove all support for half in vectors or we need an extension to control it. Draft spec here https://github.com/riscv/riscv-v-spec/pull/780 Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D121345
21 lines
999 B
LLVM
21 lines
999 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh,+m \
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; RUN: -regalloc=fast -verify-machineinstrs < %s | FileCheck %s
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; This test previously crashed with an error "ran out of registers during register allocation"
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declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32)
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define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl) {
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; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
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; CHECK-NEXT: vmv4r.v v12, v8
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; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
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; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
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ret void
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}
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