85e42db1b6
Instead of having a test for i32 XLen and i64 XLen, use sed to replace iXLen with i32/i64 before running llc. This change updates tests for intrinsics that operate exclusively on mask values. It removes over 4000 lines worth of test content. More merging will come in future changes. Differential Revision: https://reviews.llvm.org/D117968
140 lines
4.9 KiB
LLVM
140 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
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; RUN: -verify-machineinstrs | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
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; RUN: -verify-machineinstrs | FileCheck %s
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declare void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, iXLen);
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define void @intrinsic_vsm_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vsm_v_nxv1i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
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; CHECK-NEXT: vsm.v v0, (a0)
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, iXLen %2)
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ret void
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}
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declare void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, iXLen);
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define void @intrinsic_vsm_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vsm_v_nxv2i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
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; CHECK-NEXT: vsm.v v0, (a0)
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, iXLen %2)
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ret void
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}
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declare void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, iXLen);
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define void @intrinsic_vsm_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vsm_v_nxv4i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
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; CHECK-NEXT: vsm.v v0, (a0)
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, iXLen %2)
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ret void
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}
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declare void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, iXLen);
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define void @intrinsic_vsm_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vsm_v_nxv8i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
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; CHECK-NEXT: vsm.v v0, (a0)
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, iXLen %2)
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ret void
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}
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declare void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, iXLen);
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define void @intrinsic_vsm_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vsm_v_nxv16i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
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; CHECK-NEXT: vsm.v v0, (a0)
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, iXLen %2)
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ret void
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}
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declare void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, iXLen);
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define void @intrinsic_vsm_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vsm_v_nxv32i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
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; CHECK-NEXT: vsm.v v0, (a0)
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, iXLen %2)
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ret void
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}
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declare void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, iXLen);
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define void @intrinsic_vsm_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, iXLen %2) nounwind {
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; CHECK-LABEL: intrinsic_vsm_v_nxv64i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
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; CHECK-NEXT: vsm.v v0, (a0)
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, iXLen %2)
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ret void
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}
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declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
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<vscale x 1 x i16>,
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<vscale x 1 x i16>,
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iXLen);
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; Make sure we can use the vsetvli from the producing instruction.
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define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, iXLen %3) nounwind {
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; CHECK-LABEL: test_vsetvli_i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
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; CHECK-NEXT: vmseq.vv v8, v8, v9
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; CHECK-NEXT: vsm.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
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<vscale x 1 x i16> %0,
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<vscale x 1 x i16> %1,
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iXLen %3)
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call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, iXLen %3)
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ret void
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}
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declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
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<vscale x 1 x i32>,
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<vscale x 1 x i32>,
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iXLen);
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define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, iXLen %3) nounwind {
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; CHECK-LABEL: test_vsetvli_i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
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; CHECK-NEXT: vmseq.vv v8, v8, v9
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; CHECK-NEXT: vsm.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
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<vscale x 1 x i32> %0,
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<vscale x 1 x i32> %1,
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iXLen %3)
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call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, iXLen %3)
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ret void
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}
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