091244023a
Currently when tail predicating loops, vpt blocks need to be created with the vctp predicate in case we need to revert to non-tail predicated form. This has the unfortunate side effect of severely hampering post-ra scheduling at times as the instructions are already stuck in vpt blocks, not allowed to be independently ordered. This patch addresses that by just moving the creation of VPT blocks later in the pipeline, after post-ra scheduling has been performed. This allows more optimal scheduling post-ra before the vpt blocks are created, leading to more optimal tail predicated loops. Differential Revision: https://reviews.llvm.org/D113094
240 lines
10 KiB
LLVM
240 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=enabled %s -o - | \
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; RUN: FileCheck %s --check-prefix=ENABLED
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;
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; Forcing tail-predication should not be necessary here, so we check the same
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; ENABLED label as the run above:
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=force-enabled %s -o - | \
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; RUN: FileCheck %s --check-prefix=ENABLED
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;
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=enabled-no-reductions %s -o - | \
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; RUN: FileCheck %s --check-prefix=NOREDUCTIONS
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;
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -tail-predication=force-enabled-no-reductions %s -o - | \
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; RUN: FileCheck %s --check-prefix=NOREDUCTIONS
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define dso_local void @varying_outer_2d_reduction(i16* nocapture readonly %Input, i16* nocapture %Output, i16 signext %Size, i16 signext %N, i16 signext %Scale) local_unnamed_addr {
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; ENABLED-LABEL: varying_outer_2d_reduction:
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; ENABLED: @ %bb.0: @ %entry
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; ENABLED-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
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; ENABLED-NEXT: sub sp, #4
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; ENABLED-NEXT: cmp r3, #1
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; ENABLED-NEXT: str r0, [sp] @ 4-byte Spill
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; ENABLED-NEXT: blt .LBB0_8
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; ENABLED-NEXT: @ %bb.1: @ %for.body.lr.ph
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; ENABLED-NEXT: ldr r0, [sp, #36]
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; ENABLED-NEXT: add.w r12, r2, #3
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; ENABLED-NEXT: ldr.w r10, [sp] @ 4-byte Reload
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; ENABLED-NEXT: mov.w r8, #0
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; ENABLED-NEXT: mov r9, r12
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; ENABLED-NEXT: uxth r0, r0
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; ENABLED-NEXT: rsbs r5, r0, #0
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; ENABLED-NEXT: b .LBB0_4
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; ENABLED-NEXT: .LBB0_2: @ in Loop: Header=BB0_4 Depth=1
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; ENABLED-NEXT: movs r0, #0
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; ENABLED-NEXT: .LBB0_3: @ %for.end
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; ENABLED-NEXT: @ in Loop: Header=BB0_4 Depth=1
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; ENABLED-NEXT: lsrs r0, r0, #16
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; ENABLED-NEXT: sub.w r9, r9, #1
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; ENABLED-NEXT: strh.w r0, [r1, r8, lsl #1]
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; ENABLED-NEXT: add.w r8, r8, #1
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; ENABLED-NEXT: add.w r10, r10, #2
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; ENABLED-NEXT: cmp r8, r3
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; ENABLED-NEXT: beq .LBB0_8
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; ENABLED-NEXT: .LBB0_4: @ %for.body
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; ENABLED-NEXT: @ =>This Loop Header: Depth=1
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; ENABLED-NEXT: @ Child Loop BB0_6 Depth 2
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; ENABLED-NEXT: cmp r2, r8
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; ENABLED-NEXT: ble .LBB0_2
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; ENABLED-NEXT: @ %bb.5: @ %vector.ph
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; ENABLED-NEXT: @ in Loop: Header=BB0_4 Depth=1
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; ENABLED-NEXT: bic r0, r9, #3
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; ENABLED-NEXT: movs r7, #1
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; ENABLED-NEXT: subs r0, #4
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; ENABLED-NEXT: sub.w r4, r2, r8
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; ENABLED-NEXT: vmov.i32 q1, #0x0
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; ENABLED-NEXT: add.w r6, r7, r0, lsr #2
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; ENABLED-NEXT: sub.w r0, r12, r8
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; ENABLED-NEXT: bic r0, r0, #3
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; ENABLED-NEXT: subs r0, #4
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; ENABLED-NEXT: add.w r0, r7, r0, lsr #2
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; ENABLED-NEXT: mov r7, r10
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; ENABLED-NEXT: dls lr, r0
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; ENABLED-NEXT: ldr r0, [sp] @ 4-byte Reload
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; ENABLED-NEXT: .LBB0_6: @ %vector.body
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; ENABLED-NEXT: @ Parent Loop BB0_4 Depth=1
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; ENABLED-NEXT: @ => This Inner Loop Header: Depth=2
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; ENABLED-NEXT: vctp.32 r4
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; ENABLED-NEXT: vmov q0, q1
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; ENABLED-NEXT: vpstt
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; ENABLED-NEXT: vldrht.s32 q1, [r0], #8
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; ENABLED-NEXT: vldrht.s32 q2, [r7], #8
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; ENABLED-NEXT: mov lr, r6
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; ENABLED-NEXT: subs r6, #1
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; ENABLED-NEXT: vmul.i32 q1, q2, q1
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; ENABLED-NEXT: subs r4, #4
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; ENABLED-NEXT: vshl.s32 q1, r5
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; ENABLED-NEXT: vadd.i32 q1, q1, q0
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; ENABLED-NEXT: le lr, .LBB0_6
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; ENABLED-NEXT: @ %bb.7: @ %middle.block
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; ENABLED-NEXT: @ in Loop: Header=BB0_4 Depth=1
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; ENABLED-NEXT: vpsel q0, q1, q0
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; ENABLED-NEXT: vaddv.u32 r0, q0
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; ENABLED-NEXT: b .LBB0_3
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; ENABLED-NEXT: .LBB0_8: @ %for.end17
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; ENABLED-NEXT: add sp, #4
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; ENABLED-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
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;
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; NOREDUCTIONS-LABEL: varying_outer_2d_reduction:
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; NOREDUCTIONS: @ %bb.0: @ %entry
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; NOREDUCTIONS-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
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; NOREDUCTIONS-NEXT: sub sp, #4
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; NOREDUCTIONS-NEXT: cmp r3, #1
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; NOREDUCTIONS-NEXT: str r0, [sp] @ 4-byte Spill
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; NOREDUCTIONS-NEXT: blt .LBB0_8
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; NOREDUCTIONS-NEXT: @ %bb.1: @ %for.body.lr.ph
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; NOREDUCTIONS-NEXT: ldr r0, [sp, #36]
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; NOREDUCTIONS-NEXT: add.w r12, r2, #3
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; NOREDUCTIONS-NEXT: ldr.w r10, [sp] @ 4-byte Reload
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; NOREDUCTIONS-NEXT: mov.w r8, #0
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; NOREDUCTIONS-NEXT: mov r9, r12
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; NOREDUCTIONS-NEXT: uxth r0, r0
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; NOREDUCTIONS-NEXT: rsbs r5, r0, #0
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; NOREDUCTIONS-NEXT: b .LBB0_4
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; NOREDUCTIONS-NEXT: .LBB0_2: @ in Loop: Header=BB0_4 Depth=1
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; NOREDUCTIONS-NEXT: movs r0, #0
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; NOREDUCTIONS-NEXT: .LBB0_3: @ %for.end
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; NOREDUCTIONS-NEXT: @ in Loop: Header=BB0_4 Depth=1
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; NOREDUCTIONS-NEXT: lsrs r0, r0, #16
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; NOREDUCTIONS-NEXT: sub.w r9, r9, #1
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; NOREDUCTIONS-NEXT: strh.w r0, [r1, r8, lsl #1]
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; NOREDUCTIONS-NEXT: add.w r8, r8, #1
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; NOREDUCTIONS-NEXT: add.w r10, r10, #2
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; NOREDUCTIONS-NEXT: cmp r8, r3
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; NOREDUCTIONS-NEXT: beq .LBB0_8
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; NOREDUCTIONS-NEXT: .LBB0_4: @ %for.body
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; NOREDUCTIONS-NEXT: @ =>This Loop Header: Depth=1
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; NOREDUCTIONS-NEXT: @ Child Loop BB0_6 Depth 2
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; NOREDUCTIONS-NEXT: cmp r2, r8
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; NOREDUCTIONS-NEXT: ble .LBB0_2
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; NOREDUCTIONS-NEXT: @ %bb.5: @ %vector.ph
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; NOREDUCTIONS-NEXT: @ in Loop: Header=BB0_4 Depth=1
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; NOREDUCTIONS-NEXT: bic r0, r9, #3
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; NOREDUCTIONS-NEXT: movs r7, #1
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; NOREDUCTIONS-NEXT: subs r0, #4
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; NOREDUCTIONS-NEXT: sub.w r4, r2, r8
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; NOREDUCTIONS-NEXT: vmov.i32 q1, #0x0
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; NOREDUCTIONS-NEXT: add.w r6, r7, r0, lsr #2
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; NOREDUCTIONS-NEXT: sub.w r0, r12, r8
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; NOREDUCTIONS-NEXT: bic r0, r0, #3
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; NOREDUCTIONS-NEXT: subs r0, #4
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; NOREDUCTIONS-NEXT: add.w r0, r7, r0, lsr #2
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; NOREDUCTIONS-NEXT: mov r7, r10
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; NOREDUCTIONS-NEXT: dls lr, r0
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; NOREDUCTIONS-NEXT: ldr r0, [sp] @ 4-byte Reload
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; NOREDUCTIONS-NEXT: .LBB0_6: @ %vector.body
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; NOREDUCTIONS-NEXT: @ Parent Loop BB0_4 Depth=1
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; NOREDUCTIONS-NEXT: @ => This Inner Loop Header: Depth=2
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; NOREDUCTIONS-NEXT: vctp.32 r4
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; NOREDUCTIONS-NEXT: vmov q0, q1
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; NOREDUCTIONS-NEXT: vpstt
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; NOREDUCTIONS-NEXT: vldrht.s32 q1, [r0], #8
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; NOREDUCTIONS-NEXT: vldrht.s32 q2, [r7], #8
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; NOREDUCTIONS-NEXT: mov lr, r6
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; NOREDUCTIONS-NEXT: subs r6, #1
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; NOREDUCTIONS-NEXT: vmul.i32 q1, q2, q1
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; NOREDUCTIONS-NEXT: subs r4, #4
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; NOREDUCTIONS-NEXT: vshl.s32 q1, r5
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; NOREDUCTIONS-NEXT: vadd.i32 q1, q1, q0
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; NOREDUCTIONS-NEXT: le lr, .LBB0_6
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; NOREDUCTIONS-NEXT: @ %bb.7: @ %middle.block
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; NOREDUCTIONS-NEXT: @ in Loop: Header=BB0_4 Depth=1
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; NOREDUCTIONS-NEXT: vpsel q0, q1, q0
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; NOREDUCTIONS-NEXT: vaddv.u32 r0, q0
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; NOREDUCTIONS-NEXT: b .LBB0_3
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; NOREDUCTIONS-NEXT: .LBB0_8: @ %for.end17
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; NOREDUCTIONS-NEXT: add sp, #4
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; NOREDUCTIONS-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
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entry:
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%conv = sext i16 %N to i32
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%cmp36 = icmp sgt i16 %N, 0
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br i1 %cmp36, label %for.body.lr.ph, label %for.end17
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for.body.lr.ph: ; preds = %entry
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%conv2 = sext i16 %Size to i32
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%conv1032 = zext i16 %Scale to i32
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%i = add i32 %conv2, 3
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br label %for.body
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for.body: ; preds = %for.end, %for.body.lr.ph
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%lsr.iv51 = phi i32 [ %lsr.iv.next, %for.end ], [ %i, %for.body.lr.ph ]
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%lsr.iv46 = phi i16* [ %scevgep47, %for.end ], [ %Input, %for.body.lr.ph ]
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%i.037 = phi i32 [ 0, %for.body.lr.ph ], [ %inc16, %for.end ]
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%i1 = mul nsw i32 %i.037, -1
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%i2 = add i32 %i, %i1
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%i3 = lshr i32 %i2, 2
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%i4 = shl nuw i32 %i3, 2
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%i5 = add i32 %i4, -4
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%i6 = lshr i32 %i5, 2
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%i7 = add nuw nsw i32 %i6, 1
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%i8 = sub i32 %conv2, %i.037
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%cmp433 = icmp slt i32 %i.037, %conv2
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br i1 %cmp433, label %vector.ph, label %for.end
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vector.ph: ; preds = %for.body
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %i7)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv48 = phi i16* [ %scevgep49, %vector.body ], [ %lsr.iv46, %vector.ph ]
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%lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %Input, %vector.ph ]
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %i16, %vector.body ]
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%i9 = phi i32 [ %start, %vector.ph ], [ %i17, %vector.body ]
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%lsr.iv4850 = bitcast i16* %lsr.iv48 to <4 x i16>*
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%lsr.iv45 = bitcast i16* %lsr.iv to <4 x i16>*
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %i8)
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%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv45, i32 2, <4 x i1> %active.lane.mask, <4 x i16> undef)
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%i10 = sext <4 x i16> %wide.masked.load to <4 x i32>
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%wide.masked.load42 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv4850, i32 2, <4 x i1> %active.lane.mask, <4 x i16> undef)
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%i11 = sext <4 x i16> %wide.masked.load42 to <4 x i32>
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%i12 = mul nsw <4 x i32> %i11, %i10
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%i13 = insertelement <4 x i32> undef, i32 %conv1032, i32 0
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%i14 = shufflevector <4 x i32> %i13, <4 x i32> undef, <4 x i32> zeroinitializer
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%i15 = ashr <4 x i32> %i12, %i14
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%i16 = add <4 x i32> %i15, %vec.phi
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%index.next = add i32 %index, 4
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%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
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%scevgep49 = getelementptr i16, i16* %lsr.iv48, i32 4
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%i17 = call i32 @llvm.loop.decrement.reg.i32(i32 %i9, i32 1)
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%i18 = icmp ne i32 %i17, 0
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br i1 %i18, label %vector.body, label %middle.block
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middle.block: ; preds = %vector.body
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%i19 = select <4 x i1> %active.lane.mask, <4 x i32> %i16, <4 x i32> %vec.phi
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%i20 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %i19)
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br label %for.end
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for.end: ; preds = %middle.block, %for.body
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%Sum.0.lcssa = phi i32 [ 0, %for.body ], [ %i20, %middle.block ]
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%i21 = lshr i32 %Sum.0.lcssa, 16
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%conv13 = trunc i32 %i21 to i16
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%arrayidx14 = getelementptr inbounds i16, i16* %Output, i32 %i.037
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store i16 %conv13, i16* %arrayidx14, align 2
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%inc16 = add nuw nsw i32 %i.037, 1
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%scevgep47 = getelementptr i16, i16* %lsr.iv46, i32 1
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%lsr.iv.next = add i32 %lsr.iv51, -1
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%exitcond39 = icmp eq i32 %inc16, %conv
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br i1 %exitcond39, label %for.end17, label %for.body
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for.end17: ; preds = %for.end, %entry
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ret void
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}
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declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
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declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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