52e0cf9d61
This enables subreg liveness in the arm backend when MVE is present, which allows the register allocator to detect when subregister are alive/dead, compared to only acting on full registers. This can helps produce better code on MVE with the way MQPR registers are made up of SPR registers, but is especially helpful for MQQPR and MQQQQPR registers, where there are very few "registers" available and being able to split them up into subregs can help produce much better code. Differential Revision: https://reviews.llvm.org/D107642
150 lines
5.1 KiB
LLVM
150 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
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define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){
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; CHECK-LABEL: ctpop_2i64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r7, lr}
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; CHECK-NEXT: push {r4, r5, r7, lr}
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; CHECK-NEXT: vmov r1, r2, d1
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; CHECK-NEXT: mov.w lr, #1431655765
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; CHECK-NEXT: vmov r3, r4, d0
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; CHECK-NEXT: mov.w r12, #858993459
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; CHECK-NEXT: vldr s1, .LCPI0_0
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; CHECK-NEXT: vmov.f32 s3, s1
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; CHECK-NEXT: and.w r0, lr, r2, lsr #1
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; CHECK-NEXT: subs r0, r2, r0
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; CHECK-NEXT: and.w r2, r12, r0, lsr #2
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; CHECK-NEXT: bic r0, r0, #-858993460
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; CHECK-NEXT: add r0, r2
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; CHECK-NEXT: and.w r2, lr, r1, lsr #1
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; CHECK-NEXT: subs r1, r1, r2
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; CHECK-NEXT: add.w r0, r0, r0, lsr #4
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; CHECK-NEXT: and.w r2, r12, r1, lsr #2
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; CHECK-NEXT: bic r1, r1, #-858993460
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; CHECK-NEXT: add r1, r2
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; CHECK-NEXT: and.w r2, lr, r3, lsr #1
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; CHECK-NEXT: subs r2, r3, r2
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; CHECK-NEXT: bic r5, r0, #-252645136
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; CHECK-NEXT: add.w r1, r1, r1, lsr #4
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; CHECK-NEXT: mov.w r0, #16843009
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; CHECK-NEXT: and.w r3, r12, r2, lsr #2
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; CHECK-NEXT: bic r2, r2, #-858993460
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; CHECK-NEXT: add r2, r3
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; CHECK-NEXT: and.w r3, lr, r4, lsr #1
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; CHECK-NEXT: subs r3, r4, r3
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; CHECK-NEXT: bic r1, r1, #-252645136
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; CHECK-NEXT: add.w r2, r2, r2, lsr #4
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; CHECK-NEXT: muls r5, r0, r5
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; CHECK-NEXT: and.w r4, r12, r3, lsr #2
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; CHECK-NEXT: bic r3, r3, #-858993460
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; CHECK-NEXT: bic r2, r2, #-252645136
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; CHECK-NEXT: add r3, r4
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; CHECK-NEXT: muls r1, r0, r1
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; CHECK-NEXT: add.w r3, r3, r3, lsr #4
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; CHECK-NEXT: muls r2, r0, r2
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; CHECK-NEXT: bic r3, r3, #-252645136
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; CHECK-NEXT: muls r0, r3, r0
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; CHECK-NEXT: lsrs r1, r1, #24
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; CHECK-NEXT: add.w r1, r1, r5, lsr #24
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; CHECK-NEXT: lsrs r2, r2, #24
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; CHECK-NEXT: vmov s2, r1
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; CHECK-NEXT: add.w r0, r2, r0, lsr #24
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; CHECK-NEXT: vmov s0, r0
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; CHECK-NEXT: pop {r4, r5, r7, pc}
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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entry:
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%0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src)
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @ctpop_4i32_t(<4 x i32> %src){
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; CHECK-LABEL: ctpop_4i32_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-NEXT: vmov.i8 q4, #0x55
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; CHECK-NEXT: vshr.u32 q5, q0, #1
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; CHECK-NEXT: vand q4, q5, q4
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; CHECK-NEXT: vmov.i8 q3, #0x33
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; CHECK-NEXT: vsub.i32 q0, q0, q4
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; CHECK-NEXT: vmov.i8 q2, #0xf
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; CHECK-NEXT: vshr.u32 q4, q0, #2
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; CHECK-NEXT: vand q0, q0, q3
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; CHECK-NEXT: vand q4, q4, q3
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; CHECK-NEXT: vmov.i8 q1, #0x1
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; CHECK-NEXT: vadd.i32 q0, q0, q4
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; CHECK-NEXT: vshr.u32 q3, q0, #4
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; CHECK-NEXT: vadd.i32 q0, q0, q3
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; CHECK-NEXT: vand q0, q0, q2
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; CHECK-NEXT: vmul.i32 q0, q0, q1
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; CHECK-NEXT: vshr.u32 q0, q0, #24
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; CHECK-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %src)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @ctpop_8i16_t(<8 x i16> %src){
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; CHECK-LABEL: ctpop_8i16_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9, d10, d11}
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; CHECK-NEXT: vpush {d8, d9, d10, d11}
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; CHECK-NEXT: vmov.i8 q4, #0x55
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; CHECK-NEXT: vshr.u16 q5, q0, #1
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; CHECK-NEXT: vand q4, q5, q4
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; CHECK-NEXT: vmov.i8 q3, #0x33
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; CHECK-NEXT: vsub.i16 q0, q0, q4
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; CHECK-NEXT: vmov.i8 q2, #0xf
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; CHECK-NEXT: vshr.u16 q4, q0, #2
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; CHECK-NEXT: vand q0, q0, q3
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; CHECK-NEXT: vand q4, q4, q3
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; CHECK-NEXT: vmov.i8 q1, #0x1
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; CHECK-NEXT: vadd.i16 q0, q0, q4
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; CHECK-NEXT: vshr.u16 q3, q0, #4
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; CHECK-NEXT: vadd.i16 q0, q0, q3
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; CHECK-NEXT: vand q0, q0, q2
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; CHECK-NEXT: vmul.i16 q0, q0, q1
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; CHECK-NEXT: vshr.u16 q0, q0, #8
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; CHECK-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %src)
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @ctpop_16i8_t(<16 x i8> %src){
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; CHECK-LABEL: ctpop_16i8_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: vmov.i8 q3, #0x55
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; CHECK-NEXT: vshr.u8 q4, q0, #1
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; CHECK-NEXT: vand q3, q4, q3
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; CHECK-NEXT: vmov.i8 q2, #0x33
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; CHECK-NEXT: vsub.i8 q0, q0, q3
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; CHECK-NEXT: vmov.i8 q1, #0xf
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; CHECK-NEXT: vshr.u8 q3, q0, #2
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; CHECK-NEXT: vand q0, q0, q2
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; CHECK-NEXT: vand q3, q3, q2
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; CHECK-NEXT: vadd.i8 q0, q0, q3
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; CHECK-NEXT: vshr.u8 q2, q0, #4
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; CHECK-NEXT: vadd.i8 q0, q0, q2
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %src)
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ret <16 x i8> %0
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}
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declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
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declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
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declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
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declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)
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