e7dc083a41
It turns our that the BranchFolder and IfCvt does not like unanalyzable
branches that fall-through. This means that removing the unconditional
branches from the end of tail predicated instruction can run into
asserts and verifier issues.
This effectively reverts 372eb2bbb6, but
adds handling to t2DoLoopEndDec which are not branches, so can be safely
skipped.
75 lines
3.2 KiB
LLVM
75 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedldst -tail-predication=force-enabled %s -o - | FileCheck %s
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define arm_aapcs_vfpcc void @gather_inc_v4i32_simple(i32* noalias nocapture readonly %data, i32* noalias nocapture %dst, i32 %n) {
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; CHECK-LABEL: gather_inc_v4i32_simple:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: cmp r2, #1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: poplt {r4, pc}
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; CHECK-NEXT: .LBB0_1: @ %vector.ph.preheader
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; CHECK-NEXT: bic r12, r2, #3
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; CHECK-NEXT: movs r3, #1
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; CHECK-NEXT: sub.w lr, r12, #4
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; CHECK-NEXT: add.w r4, r3, lr, lsr #2
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; CHECK-NEXT: adr r3, .LCPI0_0
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; CHECK-NEXT: vldrw.u32 q0, [r3]
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: .LBB0_2: @ %vector.ph
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; CHECK-NEXT: @ =>This Loop Header: Depth=1
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; CHECK-NEXT: @ Child Loop BB0_3 Depth 2
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; CHECK-NEXT: dls lr, r4
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: vmov q1, q0
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; CHECK-NEXT: .LBB0_3: @ %vector.body
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; CHECK-NEXT: @ Parent Loop BB0_2 Depth=1
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; CHECK-NEXT: @ => This Inner Loop Header: Depth=2
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; CHECK-NEXT: vldrw.u32 q2, [q1, #16]!
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; CHECK-NEXT: vstrb.8 q2, [r0], #16
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; CHECK-NEXT: le lr, .LBB0_3
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; CHECK-NEXT: @ %bb.4: @ %middle.block
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; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
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; CHECK-NEXT: cmp r12, r2
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; CHECK-NEXT: bne .LBB0_2
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; CHECK-NEXT: @ %bb.5: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r4, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.6:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long 4294967280 @ 0xfffffff0
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; CHECK-NEXT: .long 4294967284 @ 0xfffffff4
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; CHECK-NEXT: .long 4294967288 @ 0xfffffff8
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; CHECK-NEXT: .long 4294967292 @ 0xfffffffc
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entry:
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%cmp22 = icmp sgt i32 %n, 0
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br i1 %cmp22, label %vector.ph, label %for.cond.cleanup
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vector.ph: ; preds = %for.body.preheader
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%n.vec = and i32 %n, -4
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%vec.ind = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %vector.ph ], [ %vec.ind.next, %vector.body ]
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%0 = getelementptr inbounds i32, i32* %data, <4 x i32> %vec.ind
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%wide.masked.gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %0, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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%1 = getelementptr inbounds i32, i32* %dst, i32 %index
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%2 = bitcast i32* %1 to <4 x i32>*
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store <4 x i32> %wide.masked.gather, <4 x i32>* %2, align 4
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%index.next = add i32 %index, 4
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%vec.ind.next = add <4 x i32> %vec.ind, <i32 4, i32 4, i32 4, i32 4>
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%3 = icmp eq i32 %index.next, %n.vec
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br i1 %3, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%cmp.n = icmp eq i32 %n.vec, %n
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br i1 %cmp.n, label %for.cond.cleanup, label %vector.ph
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for.cond.cleanup: ; preds = %for.body, %middle.block, %entry
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ret void
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}
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declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
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