6bd8f114c8
Some MVE instructions have qr variants that take a Q and R register, splatting the R register for each lane. This is usually handled fine for standard splats as we sink the splat into the loop and combine the resulting dup into the qr instruction. It does not work for constant splats though, as we generate a vmovimm or constant pool load instead. This intercepts that, generating a vdup of the constant instead where we can turn the result into a qr instruction variant. Differential Revision: https://reviews.llvm.org/D115242
275 lines
12 KiB
LLVM
275 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp --arm-memtransfer-tploop=allow -enable-arm-maskedgatscat=false -verify-machineinstrs %s -o - | FileCheck %s
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; verify-machineinstrs previously caught the incorrect use of QPR in the stack reloads.
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define arm_aapcs_vfpcc void @k() {
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; CHECK-LABEL: k:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
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; CHECK-NEXT: .pad #4
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; CHECK-NEXT: sub sp, #4
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: adr.w r8, .LCPI0_0
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; CHECK-NEXT: adr.w r9, .LCPI0_1
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; CHECK-NEXT: vldrw.u32 q6, [r8]
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; CHECK-NEXT: vldrw.u32 q5, [r9]
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; CHECK-NEXT: vmov.i32 q0, #0x1
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; CHECK-NEXT: vmov.i8 q1, #0x0
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; CHECK-NEXT: vmov.i8 q2, #0xff
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; CHECK-NEXT: vmov.i16 q3, #0x6
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; CHECK-NEXT: vmov.i16 q4, #0x3
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: .LBB0_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vand q6, q6, q0
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; CHECK-NEXT: vand q5, q5, q0
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; CHECK-NEXT: vcmp.i32 eq, q6, zr
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; CHECK-NEXT: cmp.w r12, #0
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; CHECK-NEXT: vpsel q6, q2, q1
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; CHECK-NEXT: vcmp.i32 eq, q5, zr
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; CHECK-NEXT: vpsel q5, q2, q1
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; CHECK-NEXT: vmov r4, r0, d12
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; CHECK-NEXT: vmov r3, r6, d10
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; CHECK-NEXT: vmov r1, r2, d11
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; CHECK-NEXT: vmov.16 q5[0], r3
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; CHECK-NEXT: vmov.16 q5[1], r6
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; CHECK-NEXT: vmov r5, r7, d13
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; CHECK-NEXT: vmov.16 q5[2], r1
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; CHECK-NEXT: vmov.16 q5[3], r2
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; CHECK-NEXT: vmov.16 q5[4], r4
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; CHECK-NEXT: vmov.16 q5[5], r0
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; CHECK-NEXT: vmov.16 q5[6], r5
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; CHECK-NEXT: vmov.16 q5[7], r7
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; CHECK-NEXT: vcmp.i16 ne, q5, zr
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; CHECK-NEXT: vmov.i32 q5, #0x0
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; CHECK-NEXT: vpsel q6, q4, q3
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; CHECK-NEXT: vstrh.16 q6, [r0]
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; CHECK-NEXT: vmov q6, q5
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; CHECK-NEXT: bne .LBB0_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond4.preheader
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; CHECK-NEXT: movs r6, #0
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; CHECK-NEXT: cbnz r6, .LBB0_5
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; CHECK-NEXT: .LBB0_3: @ %for.body10
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cbnz r6, .LBB0_4
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; CHECK-NEXT: le .LBB0_3
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; CHECK-NEXT: .LBB0_4: @ %for.cond4.loopexit
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; CHECK-NEXT: bl l
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; CHECK-NEXT: .LBB0_5: @ %vector.body105.preheader
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; CHECK-NEXT: vldrw.u32 q0, [r8]
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; CHECK-NEXT: vldrw.u32 q1, [r9]
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; CHECK-NEXT: movs r0, #8
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; CHECK-NEXT: .LBB0_6: @ %vector.body105
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vadd.i32 q1, q1, r0
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: cbz r6, .LBB0_7
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; CHECK-NEXT: le .LBB0_6
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; CHECK-NEXT: .LBB0_7: @ %vector.body115.ph
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; CHECK-NEXT: vldrw.u32 q0, [r9]
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; CHECK-NEXT: movs r0, #4
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; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
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; CHECK-NEXT: @APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
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; CHECK-NEXT: .LBB0_8: @ %vector.body115
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vadd.i32 q0, q0, r0
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; CHECK-NEXT: b .LBB0_8
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.9:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long 4 @ 0x4
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; CHECK-NEXT: .long 5 @ 0x5
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; CHECK-NEXT: .long 6 @ 0x6
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; CHECK-NEXT: .long 7 @ 0x7
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; CHECK-NEXT: .LCPI0_1:
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 2 @ 0x2
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; CHECK-NEXT: .long 3 @ 0x3
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entry:
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br label %vector.body
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vector.body: ; preds = %vector.body, %entry
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%vec.ind = phi <8 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %entry ], [ zeroinitializer, %vector.body ]
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%0 = and <8 x i32> %vec.ind, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%1 = icmp eq <8 x i32> %0, zeroinitializer
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%2 = select <8 x i1> %1, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>, <8 x i16> <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
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%3 = bitcast i16* undef to <8 x i16>*
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store <8 x i16> %2, <8 x i16>* %3, align 2
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%4 = icmp eq i32 undef, 128
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br i1 %4, label %for.cond4.preheader, label %vector.body
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for.cond4.preheader: ; preds = %vector.body
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br i1 undef, label %vector.body105, label %for.body10
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for.cond4.loopexit: ; preds = %for.body10
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%call5 = call arm_aapcs_vfpcc i32 bitcast (i32 (...)* @l to i32 ()*)()
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br label %vector.body105
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for.body10: ; preds = %for.body10, %for.cond4.preheader
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%exitcond88 = icmp eq i32 undef, 7
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br i1 %exitcond88, label %for.cond4.loopexit, label %for.body10
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vector.body105: ; preds = %vector.body105, %for.cond4.loopexit, %for.cond4.preheader
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%vec.ind113 = phi <8 x i32> [ %vec.ind.next114, %vector.body105 ], [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %for.cond4.loopexit ], [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, %for.cond4.preheader ]
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%5 = and <8 x i32> %vec.ind113, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%vec.ind.next114 = add <8 x i32> %vec.ind113, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
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%6 = icmp eq i32 undef, 256
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br i1 %6, label %vector.body115.ph, label %vector.body105
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vector.body115.ph: ; preds = %vector.body105
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tail call void asm sideeffect "nop", "~{s0},~{s4},~{s8},~{s12},~{s16},~{s20},~{s24},~{s28},~{memory}"()
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br label %vector.body115
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vector.body115: ; preds = %vector.body115, %vector.body115.ph
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%vec.ind123 = phi <4 x i32> [ %vec.ind.next124, %vector.body115 ], [ <i32 0, i32 1, i32 2, i32 3>, %vector.body115.ph ]
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%7 = icmp eq <4 x i32> %vec.ind123, zeroinitializer
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%vec.ind.next124 = add <4 x i32> %vec.ind123, <i32 4, i32 4, i32 4, i32 4>
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br label %vector.body115
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}
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@a = external dso_local global i32, align 4
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@b = dso_local local_unnamed_addr global i32 ptrtoint (i32* @a to i32), align 4
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@c = dso_local global i32 2, align 4
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@d = dso_local global i32 2, align 4
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define dso_local i32 @e() #0 {
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; CHECK-LABEL: e:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: .pad #408
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; CHECK-NEXT: sub sp, #408
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; CHECK-NEXT: movw r7, :lower16:.L_MergedGlobals
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; CHECK-NEXT: vldr s15, .LCPI1_1
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; CHECK-NEXT: movt r7, :upper16:.L_MergedGlobals
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; CHECK-NEXT: movw r2, :lower16:e
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; CHECK-NEXT: mov r4, r7
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; CHECK-NEXT: mov r3, r7
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; CHECK-NEXT: ldr r6, [r4, #8]!
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: ldr r0, [r3, #4]!
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; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
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; CHECK-NEXT: movt r2, :upper16:e
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; CHECK-NEXT: vmov r5, s15
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; CHECK-NEXT: vmov q0[2], q0[0], r4, r4
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; CHECK-NEXT: vmov s13, r3
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; CHECK-NEXT: vldr s12, .LCPI1_0
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; CHECK-NEXT: vmov q0[3], q0[1], r5, r2
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; CHECK-NEXT: vdup.32 q7, r3
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; CHECK-NEXT: vmov q6[2], q6[0], r3, r5
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; CHECK-NEXT: vstrw.32 q0, [sp, #92]
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; CHECK-NEXT: vmov q0, q7
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; CHECK-NEXT: vmov q6[3], q6[1], r3, r2
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; CHECK-NEXT: vmov q4, q7
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; CHECK-NEXT: vmov.32 q0[0], r2
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; CHECK-NEXT: vmov.32 q7[1], r2
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; CHECK-NEXT: vmov s21, r2
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; CHECK-NEXT: movs r1, #64
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; CHECK-NEXT: vmov.f32 s20, s12
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; CHECK-NEXT: str r0, [sp, #40]
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; CHECK-NEXT: vmov.f32 s22, s13
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; CHECK-NEXT: str r6, [r0]
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; CHECK-NEXT: vmov.f32 s23, s15
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; CHECK-NEXT: str r0, [r0]
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; CHECK-NEXT: vstrw.32 q5, [r0]
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; CHECK-NEXT: vstrw.32 q7, [r0]
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: vstrw.32 q6, [r0]
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; CHECK-NEXT: mov.w r8, #0
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; CHECK-NEXT: vmov q1[2], q1[0], r4, r3
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; CHECK-NEXT: vmov q2[2], q2[0], r3, r3
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; CHECK-NEXT: mov.w r12, #4
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; CHECK-NEXT: vmov q1[3], q1[1], r2, r4
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; CHECK-NEXT: vmov.f32 s14, s13
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; CHECK-NEXT: vmov q2[3], q2[1], r4, r5
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; CHECK-NEXT: vmov.32 q4[0], r8
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; CHECK-NEXT: @ implicit-def: $r2
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; CHECK-NEXT: str.w r8, [sp, #44]
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; CHECK-NEXT: vstrw.32 q3, [sp, #60]
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; CHECK-NEXT: strh.w r12, [sp, #406]
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; CHECK-NEXT: wlstp.8 lr, r1, .LBB1_2
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; CHECK-NEXT: .LBB1_1: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
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; CHECK-NEXT: vstrb.8 q0, [r2], #16
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; CHECK-NEXT: letp lr, .LBB1_1
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; CHECK-NEXT: .LBB1_2: @ %entry
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; CHECK-NEXT: vstrw.32 q1, [r0]
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; CHECK-NEXT: str.w r8, [r7]
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; CHECK-NEXT: vstrw.32 q4, [r0]
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; CHECK-NEXT: vstrw.32 q2, [r0]
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; CHECK-NEXT: str.w r12, [sp, #324]
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; CHECK-NEXT: .LBB1_3: @ %for.cond
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: b .LBB1_3
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.4:
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; CHECK-NEXT: .LCPI1_0:
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; CHECK-NEXT: .long 0x00000004 @ float 5.60519386E-45
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; CHECK-NEXT: .LCPI1_1:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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entry:
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%f = alloca i16, align 2
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%g = alloca [3 x [8 x [4 x i16*]]], align 4
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store i16 4, i16* %f, align 2
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%0 = load i32, i32* @c, align 4
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%1 = load i32, i32* @d, align 4
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%arrayinit.element7 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 0, i32 1, i32 1
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%2 = bitcast i16** %arrayinit.element7 to i32*
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store i32 %0, i32* %2, align 4
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%arrayinit.element8 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 0, i32 1, i32 2
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store i16* null, i16** %arrayinit.element8, align 4
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%3 = bitcast i16** undef to i32*
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store i32 %1, i32* %3, align 4
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%4 = bitcast i16** undef to i32*
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store i32 %0, i32* %4, align 4
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%arrayinit.element13 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 0, i32 2, i32 2
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%5 = bitcast i16** %arrayinit.element13 to <4 x i16*>*
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store <4 x i16*> <i16* inttoptr (i32 4 to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*), i16* null>, <4 x i16*>* %5, align 4
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%arrayinit.element24 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 0, i32 4, i32 2
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%6 = bitcast i16** %arrayinit.element24 to <4 x i16*>*
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store <4 x i16*> <i16* bitcast (i32* @d to i16*), i16* null, i16* bitcast (i32* @d to i16*), i16* bitcast (i32 ()* @e to i16*)>, <4 x i16*>* %6, align 4
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%7 = bitcast i16** undef to <4 x i16*>*
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store <4 x i16*> <i16* inttoptr (i32 4 to i16*), i16* bitcast (i32 ()* @e to i16*), i16* bitcast (i32* @c to i16*), i16* null>, <4 x i16*>* %7, align 4
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%8 = bitcast i16** undef to <4 x i16*>*
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store <4 x i16*> <i16* bitcast (i32* @c to i16*), i16* bitcast (i32 ()* @e to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*)>, <4 x i16*>* %8, align 4
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%9 = bitcast i16** undef to <4 x i16*>*
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store <4 x i16*> <i16* bitcast (i32 ()* @e to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*)>, <4 x i16*>* %9, align 4
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%10 = bitcast i16** undef to <4 x i16*>*
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store <4 x i16*> <i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*), i16* null, i16* bitcast (i32 ()* @e to i16*)>, <4 x i16*>* %10, align 4
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call void @llvm.memset.p0i8.i32(i8* nonnull align 4 dereferenceable(64) undef, i8 0, i32 64, i1 false)
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%11 = bitcast i16** undef to <4 x i16*>*
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store <4 x i16*> <i16* bitcast (i32* @d to i16*), i16* bitcast (i32 ()* @e to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @d to i16*)>, <4 x i16*>* %11, align 4
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%12 = bitcast i16** undef to <4 x i16*>*
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store <4 x i16*> <i16* null, i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @c to i16*)>, <4 x i16*>* %12, align 4
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%13 = bitcast i16** undef to <4 x i16*>*
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store <4 x i16*> <i16* bitcast (i32* @c to i16*), i16* bitcast (i32* @d to i16*), i16* bitcast (i32* @c to i16*), i16* null>, <4 x i16*>* %13, align 4
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%arrayinit.begin78 = getelementptr inbounds [3 x [8 x [4 x i16*]]], [3 x [8 x [4 x i16*]]]* %g, i32 0, i32 2, i32 3, i32 0
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store i16* inttoptr (i32 4 to i16*), i16** %arrayinit.begin78, align 4
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store i32 0, i32* @b, align 4
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br label %for.cond
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for.cond: ; preds = %for.cond, %entry
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br label %for.cond
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}
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; Function Attrs: argmemonly nounwind willreturn
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declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg) #1
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; Function Attrs: argmemonly nounwind willreturn
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declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg) #1
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declare arm_aapcs_vfpcc i32 @l(...)
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