255ad73424
MVE can treat v16i1, v8i1, v4i1 and v2i1 as different views onto the same 16bit VPR.P0 register, with v2i1 holding two 8 bit values for the two halves. This was never treated as a legal type in llvm in the past as there are not many 64bit instructions and no 64bit compares. There are a few instructions that could use it though, notably a VSELECT (as it can handle any size using the underlying v16i8 VPSEL), AND/OR/XOR for similar reasons, some gathers/scatter and long multiplies and VCTP64 instructions. This patch goes through and makes v2i1 a legal type, handling all the cases that fall out of that. It also makes VSELECT legal for v2i64 as a side benefit. A lot of the codegen changes as a result - usually in way that is a little better or a little worse, but still expensive. Costs can change a little too in the process, again in a way that expensive things remain expensive. A lot of the tests that changed are mainly to ensure correctness - the code can hopefully be improved in the future where it comes up in practice. The intrinsics currently remain using the v4i1 they previously did to emulate a v2i1. This will be changed in a followup patch but this one was already large enough. Differential Revision: https://reviews.llvm.org/D114449
179 lines
5.7 KiB
LLVM
179 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @build_true_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: build_true_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%s = select <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @build_false_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: build_false_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <4 x i1> <i1 0, i1 0, i1 0, i1 0>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @build_upper_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: build_upper_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov.w r0, #65280
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <4 x i1> <i1 0, i1 0, i1 1, i1 1>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <4 x i32> @build_lower_v4i1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: build_lower_v4i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #255
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <4 x i1> <i1 1, i1 1, i1 0, i1 0>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %s
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}
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define arm_aapcs_vfpcc <8 x i16> @build_true_v8i1(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: build_true_v8i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%s = select <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %s
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}
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define arm_aapcs_vfpcc <8 x i16> @build_false_v8i1(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: build_false_v8i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %s
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}
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define arm_aapcs_vfpcc <8 x i16> @build_upper_v8i1(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: build_upper_v8i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov.w r0, #65280
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <8 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %s
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}
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define arm_aapcs_vfpcc <8 x i16> @build_lower_v8i1(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: build_lower_v8i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #255
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %s
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}
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define arm_aapcs_vfpcc <16 x i8> @build_true_v16i1(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: build_true_v16i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%s = select <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %s
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}
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define arm_aapcs_vfpcc <16 x i8> @build_false_v16i1(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: build_false_v16i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %s
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}
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define arm_aapcs_vfpcc <16 x i8> @build_upper_v16i1(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: build_upper_v16i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov.w r0, #65280
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %s
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}
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define arm_aapcs_vfpcc <16 x i8> @build_lower_v16i1(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: build_lower_v16i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #255
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0>, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %s
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}
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define arm_aapcs_vfpcc <2 x i64> @build_true_v2i1(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: build_true_v2i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%s = select <2 x i1> <i1 1, i1 1>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %s
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}
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define arm_aapcs_vfpcc <2 x i64> @build_false_v2i1(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: build_false_v2i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <2 x i1> <i1 0, i1 0>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %s
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}
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define arm_aapcs_vfpcc <2 x i64> @build_upper_v2i1(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: build_upper_v2i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov.w r0, #65280
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <2 x i1> <i1 0, i1 1>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %s
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}
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define arm_aapcs_vfpcc <2 x i64> @build_lower_v2i1(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: build_lower_v2i1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r0, #255
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; CHECK-NEXT: vmsr p0, r0
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; CHECK-NEXT: vpsel q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%s = select <2 x i1> <i1 1, i1 0>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %s
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}
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