9d5af55589
This patch enables the case where we do not completely eliminate offset. Supposedly in this case we reduce live range overlap that never harms, but since there are doubts this is true, this goes as a separate change. Differential Revision: https://reviews.llvm.org/D96399 Reviewed By: reames
220 lines
7.0 KiB
LLVM
220 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s
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define i32 @test_01(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: test_01:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB0_1: ## %loop
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: subq $1, %rsi
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; CHECK-NEXT: jb LBB0_4
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; CHECK-NEXT: ## %bb.2: ## %backedge
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; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: cmpl %edx, (%rdi,%rsi,4)
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; CHECK-NEXT: jne LBB0_1
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; CHECK-NEXT: ## %bb.3: ## %failure
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; CHECK-NEXT: ud2
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; CHECK-NEXT: LBB0_4: ## %exit
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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entry:
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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%iv.next = add nsw i64 %iv, -1
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%addr = getelementptr inbounds i32, i32* %p, i64 %iv.next
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%loaded = load atomic i32, i32* %addr unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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; Similar to test_01, but we use offsetted pointer as base.
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define i32 @test_01a(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: test_01a:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB1_1: ## %loop
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: subq $1, %rsi
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; CHECK-NEXT: jb LBB1_4
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; CHECK-NEXT: ## %bb.2: ## %backedge
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; CHECK-NEXT: ## in Loop: Header=BB1_1 Depth=1
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; CHECK-NEXT: cmpl %edx, -24(%rdi,%rsi,4)
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; CHECK-NEXT: jne LBB1_1
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; CHECK-NEXT: ## %bb.3: ## %failure
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; CHECK-NEXT: ud2
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; CHECK-NEXT: LBB1_4: ## %exit
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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entry:
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%base = getelementptr inbounds i32, i32* %p, i64 -6
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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%iv.next = add nsw i64 %iv, -1
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%addr = getelementptr inbounds i32, i32* %base, i64 %iv.next
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%loaded = load atomic i32, i32* %addr unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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define i32 @test_02(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: test_02:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB2_1: ## %loop
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: subq $1, %rsi
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; CHECK-NEXT: jb LBB2_4
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; CHECK-NEXT: ## %bb.2: ## %backedge
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; CHECK-NEXT: ## in Loop: Header=BB2_1 Depth=1
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; CHECK-NEXT: cmpl %edx, (%rdi,%rsi,4)
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; CHECK-NEXT: jne LBB2_1
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; CHECK-NEXT: ## %bb.3: ## %failure
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; CHECK-NEXT: ud2
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; CHECK-NEXT: LBB2_4: ## %exit
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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entry:
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%start = add i64 %len, -1
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]
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%iv.next = add nsw i64 %iv, -1
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%iv.offset = add i64 %iv, 1
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%iv.next.offset = add i64 %iv.next, 1
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%cond_1 = icmp eq i64 %iv.offset, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset
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%loaded = load atomic i32, i32* %addr unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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define i32 @test_03(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: test_03:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: LBB3_1: ## %loop
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; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: subq $1, %rsi
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; CHECK-NEXT: jb LBB3_4
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; CHECK-NEXT: ## %bb.2: ## %backedge
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; CHECK-NEXT: ## in Loop: Header=BB3_1 Depth=1
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; CHECK-NEXT: cmpl %edx, (%rdi,%rsi,4)
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; CHECK-NEXT: jne LBB3_1
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; CHECK-NEXT: ## %bb.3: ## %failure
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; CHECK-NEXT: ud2
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; CHECK-NEXT: LBB3_4: ## %exit
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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entry:
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%start = add i64 %len, -100
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %start, %entry ]
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%iv.next = add nsw i64 %iv, -1
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%iv.offset = add i64 %iv, 100
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%iv.next.offset = add i64 %iv.next, 100
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%cond_1 = icmp eq i64 %iv.offset, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%addr = getelementptr inbounds i32, i32* %p, i64 %iv.next.offset
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%loaded = load atomic i32, i32* %addr unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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define void @test_04() {
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; CHECK-LABEL: test_04:
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; CHECK: ## %bb.0: ## %bb
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; CHECK-NEXT: ud2
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bb:
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br label %bb1
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bb1: ; preds = %bb10, %bb
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%tmp = phi i64 [ 1, %bb ], [ %tmp2, %bb10 ]
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%tmp2 = add nuw nsw i64 %tmp, 1
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%tmp6 = bitcast i8 addrspace(1)* undef to i32 addrspace(1)*
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br i1 undef, label %bb21, label %bb7
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bb7: ; preds = %bb1
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%tmp8 = add nsw i64 %tmp, -1
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%tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %tmp6, i64 %tmp8
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store atomic i32 undef, i32 addrspace(1)* %tmp9 unordered, align 4
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br label %bb11
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bb10: ; preds = %bb16
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br label %bb1
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bb11: ; preds = %bb16, %bb7
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switch i32 undef, label %bb19 [
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i32 0, label %bb17
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i32 1, label %bb16
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i32 2, label %bb15
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i32 3, label %bb14
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i32 4, label %bb12
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]
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bb12: ; preds = %bb11
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unreachable
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bb14: ; preds = %bb11
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unreachable
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bb15: ; preds = %bb11
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unreachable
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bb16: ; preds = %bb11
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br i1 undef, label %bb10, label %bb11
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bb17: ; preds = %bb11
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unreachable
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bb19: ; preds = %bb11
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unreachable
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bb21: ; preds = %bb1
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unreachable
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}
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