a3b52a9d13
This is a follow up of D99010. We didn't consider the live range of shape registers when hoist ldtilecfg. There maybe risks, e.g. we happen to insert it to an invalid range of some registers and get unexpected error. This patch fixes this problem by storing the value to corresponding stack place of ldtilecfg after all its definition immediately. This patch also fix a problem in previous code: If we don't have a ldtilecfg which dominates all AMX instructions, we cannot initialize shapes for other ldtilecfg. There're still some optimization points left. E.g. eliminate unused mov instructions, break the def-use dependency before RA etc. Reviewed By: LuoYuanke, xiangzhangllvm Differential Revision: https://reviews.llvm.org/D99966
143 lines
6.1 KiB
LLVM
143 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s --check-prefix=AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx2 -verify-machineinstrs | FileCheck %s --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -verify-machineinstrs | FileCheck %s --check-prefix=SSE2
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@buf = dso_local global [1024 x i8] zeroinitializer, align 64
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@buf2 = dso_local global [1024 x i8] zeroinitializer, align 64
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; Function Attrs: nounwind uwtable
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define dso_local void @test_api(i32 %0, i16 signext %1, i16 signext %2) {
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; AVX512-LABEL: test_api:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpxord %zmm0, %zmm0, %zmm0
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; AVX512-NEXT: vmovdqu64 %zmm0, -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: movb $1, -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: movw %si, -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: testl %edi, %edi
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; AVX512-NEXT: movsbl %sil, %eax
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; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
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; AVX512-NEXT: je .LBB0_2
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; AVX512-NEXT: # %bb.1:
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; AVX512-NEXT: movl $buf, %ecx
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; AVX512-NEXT: jmp .LBB0_3
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; AVX512-NEXT: .LBB0_2:
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; AVX512-NEXT: movl $buf2, %ecx
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; AVX512-NEXT: .LBB0_3:
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; AVX512-NEXT: movl $32, %edi
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; AVX512-NEXT: tileloadd (%rcx,%rdi), %tmm0
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; AVX512-NEXT: tileloadd (%rcx,%rdi), %tmm2
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; AVX512-NEXT: tileloadd (%rcx,%rdi), %tmm1
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; AVX512-NEXT: tdpbssd %tmm2, %tmm0, %tmm1
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; AVX512-NEXT: movl $buf, %ecx
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; AVX512-NEXT: movl $32, %esi
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; AVX512-NEXT: tilestored %tmm1, (%rcx,%rsi)
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; AVX512-NEXT: tilerelease
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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;
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; AVX2-LABEL: test_api:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vxorps %ymm0, %ymm0, %ymm0
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; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: vmovups %ymm0, -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: movb $1, -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: movw %si, -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: testl %edi, %edi
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; AVX2-NEXT: movsbl %sil, %eax
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; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
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; AVX2-NEXT: je .LBB0_2
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; AVX2-NEXT: # %bb.1:
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; AVX2-NEXT: movl $buf, %ecx
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; AVX2-NEXT: jmp .LBB0_3
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; AVX2-NEXT: .LBB0_2:
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; AVX2-NEXT: movl $buf2, %ecx
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; AVX2-NEXT: .LBB0_3:
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; AVX2-NEXT: movl $32, %edi
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; AVX2-NEXT: tileloadd (%rcx,%rdi), %tmm0
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; AVX2-NEXT: tileloadd (%rcx,%rdi), %tmm2
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; AVX2-NEXT: tileloadd (%rcx,%rdi), %tmm1
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; AVX2-NEXT: tdpbssd %tmm2, %tmm0, %tmm1
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; AVX2-NEXT: movl $buf, %ecx
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; AVX2-NEXT: movl $32, %esi
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; AVX2-NEXT: tilestored %tmm1, (%rcx,%rsi)
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; AVX2-NEXT: tilerelease
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; SSE2-LABEL: test_api:
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; SSE2: # %bb.0:
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; SSE2-NEXT: xorps %xmm0, %xmm0
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; SSE2-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movups %xmm0, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movb $1, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movw %si, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: testl %edi, %edi
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; SSE2-NEXT: movsbl %sil, %eax
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; SSE2-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
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; SSE2-NEXT: je .LBB0_2
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; SSE2-NEXT: # %bb.1:
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; SSE2-NEXT: movl $buf, %ecx
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; SSE2-NEXT: jmp .LBB0_3
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; SSE2-NEXT: .LBB0_2:
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; SSE2-NEXT: movl $buf2, %ecx
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; SSE2-NEXT: .LBB0_3:
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; SSE2-NEXT: movl $32, %edi
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; SSE2-NEXT: tileloadd (%rcx,%rdi), %tmm0
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; SSE2-NEXT: tileloadd (%rcx,%rdi), %tmm2
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; SSE2-NEXT: tileloadd (%rcx,%rdi), %tmm1
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; SSE2-NEXT: tdpbssd %tmm2, %tmm0, %tmm1
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; SSE2-NEXT: movl $buf, %ecx
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; SSE2-NEXT: movl $32, %esi
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; SSE2-NEXT: tilestored %tmm1, (%rcx,%rsi)
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; SSE2-NEXT: tilerelease
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; SSE2-NEXT: retq
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%4 = icmp eq i32 %0, 0
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%5 = shl i16 %1, 8
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%6 = ashr exact i16 %5, 8
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br i1 %4, label %11, label %7
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7: ; preds = %3
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%8 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %6, i16 %1, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%9 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %6, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%10 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %6, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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br label %15
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11: ; preds = %3
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%12 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %6, i16 %1, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf2, i64 0, i64 0), i64 32)
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%13 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %6, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf2, i64 0, i64 0), i64 32)
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%14 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %6, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf2, i64 0, i64 0), i64 32)
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br label %15
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15: ; preds = %11, %7
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%16 = phi x86_amx [ %12, %11 ], [ %8, %7 ]
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%17 = phi x86_amx [ %13, %11 ], [ %9, %7 ]
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%18 = phi x86_amx [ %14, %11 ], [ %10, %7 ]
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%19 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %6, i16 %2, i16 %1, x86_amx %18, x86_amx %16, x86_amx %17)
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tail call void @llvm.x86.tilestored64.internal(i16 %6, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32, x86_amx %19)
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ret void
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}
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declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, i8*, i64)
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declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
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declare void @llvm.x86.tilestored64.internal(i16, i16, i8*, i64, x86_amx)
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