773771ba38
Register allocation may spill virtual registers to the stack, which can increase alignment requirements of the stack frame. If the the function did not require stack realignment before register allocation, the registers required to do so may not be reserved/available. This results in a stack frame that requires realignment but can not be realigned. Instead, only increase the alignment of the stack if we are still able to realign. The register SpillAlignment will be ignored if we can't realign, and the backend will be responsible for emitting the correct unaligned loads and stores. This seems to be the assumed behaviour already, e.g. ARMBaseInstrInfo::storeRegToStackSlot and X86InstrInfo::storeRegToStackSlot are both `canRealignStack` aware. Differential Revision: https://reviews.llvm.org/D103602
105 lines
6.1 KiB
LLVM
105 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx512f -verify-machineinstrs | FileCheck %s
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@buf = dso_local global [1024 x i8] zeroinitializer, align 64
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@buf2 = dso_local global [1024 x i8] zeroinitializer, align 64
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define dso_local void @test_api(i32 %0, i16 signext %1, i16 signext %2) nounwind {
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; CHECK-LABEL: test_api:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subq $968, %rsp # imm = 0x3C8
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; CHECK-NEXT: vpxord %zmm0, %zmm0, %zmm0
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; CHECK-NEXT: vmovdqu64 %zmm0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb %sil, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw %si, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb %sil, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb %dl, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb %dl, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb %sil, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb %dl, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb %sil, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb %dl, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movl $buf, %r8d
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; CHECK-NEXT: movl $32, %eax
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm1
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm1
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; CHECK-NEXT: movabsq $64, %rcx
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; CHECK-NEXT: tilestored %tmm1, -64(%rsp,%rcx) # 1024-byte Folded Spill
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm3
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm4
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm2
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm5
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm0
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: je .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm6
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm7
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; CHECK-NEXT: tileloadd (%r8,%rax), %tmm1
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; CHECK-NEXT: jmp .LBB0_3
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: movl $buf2, %ecx
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; CHECK-NEXT: tileloadd (%rcx,%rax), %tmm6
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; CHECK-NEXT: tileloadd (%rcx,%rax), %tmm7
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; CHECK-NEXT: tileloadd (%rcx,%rax), %tmm1
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: tdpbssd %tmm7, %tmm6, %tmm1
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tileloadd -64(%rsp,%rax), %tmm7 # 1024-byte Folded Reload
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; CHECK-NEXT: tdpbssd %tmm7, %tmm1, %tmm3
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; CHECK-NEXT: tdpbssd %tmm4, %tmm3, %tmm2
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; CHECK-NEXT: tdpbssd %tmm5, %tmm2, %tmm0
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; CHECK-NEXT: movl $buf, %eax
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; CHECK-NEXT: movl $32, %ecx
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; CHECK-NEXT: tilestored %tmm0, (%rax,%rcx)
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; CHECK-NEXT: addq $968, %rsp # imm = 0x3C8
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; CHECK-NEXT: tilerelease
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%4 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %1, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%5 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %1, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%6 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %1, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%7 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %2, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%8 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %2, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%9 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %2, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%10 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %2, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%11 = icmp eq i32 %0, 0
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br i1 %11, label %16, label %12
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12: ; preds = %3
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%13 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %1, i16 %1, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%14 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %1, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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%15 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %1, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32)
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br label %20
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16: ; preds = %3
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%17 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %1, i16 %1, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf2, i64 0, i64 0), i64 32)
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%18 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %1, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf2, i64 0, i64 0), i64 32)
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%19 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %1, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf2, i64 0, i64 0), i64 32)
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br label %20
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20: ; preds = %16, %12
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%21 = phi x86_amx [ %17, %16 ], [ %13, %12 ]
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%22 = phi x86_amx [ %18, %16 ], [ %14, %12 ]
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%23 = phi x86_amx [ %19, %16 ], [ %15, %12 ]
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%24 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %1, i16 %2, i16 %1, x86_amx %23, x86_amx %21, x86_amx %22)
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%25 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %1, i16 %2, i16 %2, x86_amx %6, x86_amx %24, x86_amx %5)
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%26 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %1, i16 %2, i16 %2, x86_amx %8, x86_amx %25, x86_amx %7)
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%27 = tail call x86_amx @llvm.x86.tdpbssd.internal(i16 %2, i16 %2, i16 %2, x86_amx %10, x86_amx %26, x86_amx %9)
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tail call void @llvm.x86.tilestored64.internal(i16 %2, i16 %2, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64 0, i64 0), i64 32, x86_amx %27)
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ret void
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}
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declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, i8*, i64)
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declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
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declare void @llvm.x86.tilestored64.internal(i16, i16, i8*, i64, x86_amx)
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