59fa435ea6
This demonstrates a possible fix for PR48760 - for compares with constants, canonicalize the SGT/UGT condition code to use SGE/UGE which should reduce the number of EFLAGs bits we need to read. As discussed on PR48760, some EFLAG bits are treated independently which can require additional uops to merge together for certain CMOVcc/SETcc/etc. modes. I've limited this to cases where the constant increment doesn't result in a larger encoding or additional i64 constant materializations. Differential Revision: https://reviews.llvm.org/D101074
347 lines
10 KiB
LLVM
347 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=CHECK --check-prefix=FASTINCDEC
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; RUN: llc < %s -mtriple=x86_64-- -mattr=slow-incdec | FileCheck %s --check-prefix=CHECK --check-prefix=SLOWINCDEC
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define i32 @test_add_1_cmov_slt(i64* %p, i32 %a0, i32 %a1) #0 {
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; FASTINCDEC-LABEL: test_add_1_cmov_slt:
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; FASTINCDEC: # %bb.0: # %entry
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; FASTINCDEC-NEXT: movl %esi, %eax
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; FASTINCDEC-NEXT: lock incq (%rdi)
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; FASTINCDEC-NEXT: cmovgl %edx, %eax
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; FASTINCDEC-NEXT: retq
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;
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; SLOWINCDEC-LABEL: test_add_1_cmov_slt:
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; SLOWINCDEC: # %bb.0: # %entry
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; SLOWINCDEC-NEXT: movl %esi, %eax
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; SLOWINCDEC-NEXT: lock addq $1, (%rdi)
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; SLOWINCDEC-NEXT: cmovgl %edx, %eax
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; SLOWINCDEC-NEXT: retq
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entry:
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%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
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%tmp1 = icmp slt i64 %tmp0, 0
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%tmp2 = select i1 %tmp1, i32 %a0, i32 %a1
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ret i32 %tmp2
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}
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define i32 @test_add_1_cmov_sge(i64* %p, i32 %a0, i32 %a1) #0 {
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; FASTINCDEC-LABEL: test_add_1_cmov_sge:
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; FASTINCDEC: # %bb.0: # %entry
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; FASTINCDEC-NEXT: movl %esi, %eax
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; FASTINCDEC-NEXT: lock incq (%rdi)
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; FASTINCDEC-NEXT: cmovlel %edx, %eax
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; FASTINCDEC-NEXT: retq
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;
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; SLOWINCDEC-LABEL: test_add_1_cmov_sge:
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; SLOWINCDEC: # %bb.0: # %entry
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; SLOWINCDEC-NEXT: movl %esi, %eax
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; SLOWINCDEC-NEXT: lock addq $1, (%rdi)
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; SLOWINCDEC-NEXT: cmovlel %edx, %eax
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; SLOWINCDEC-NEXT: retq
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entry:
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%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
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%tmp1 = icmp sge i64 %tmp0, 0
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%tmp2 = select i1 %tmp1, i32 %a0, i32 %a1
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ret i32 %tmp2
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}
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define i32 @test_sub_1_cmov_sle(i64* %p, i32 %a0, i32 %a1) #0 {
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; FASTINCDEC-LABEL: test_sub_1_cmov_sle:
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; FASTINCDEC: # %bb.0: # %entry
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; FASTINCDEC-NEXT: movl %esi, %eax
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; FASTINCDEC-NEXT: lock decq (%rdi)
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; FASTINCDEC-NEXT: cmovgel %edx, %eax
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; FASTINCDEC-NEXT: retq
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;
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; SLOWINCDEC-LABEL: test_sub_1_cmov_sle:
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; SLOWINCDEC: # %bb.0: # %entry
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; SLOWINCDEC-NEXT: movl %esi, %eax
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; SLOWINCDEC-NEXT: lock subq $1, (%rdi)
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; SLOWINCDEC-NEXT: cmovgel %edx, %eax
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; SLOWINCDEC-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
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%tmp1 = icmp sle i64 %tmp0, 0
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%tmp2 = select i1 %tmp1, i32 %a0, i32 %a1
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ret i32 %tmp2
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}
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define i32 @test_sub_1_cmov_sgt(i64* %p, i32 %a0, i32 %a1) #0 {
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; FASTINCDEC-LABEL: test_sub_1_cmov_sgt:
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; FASTINCDEC: # %bb.0: # %entry
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; FASTINCDEC-NEXT: movl %esi, %eax
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; FASTINCDEC-NEXT: lock decq (%rdi)
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; FASTINCDEC-NEXT: cmovll %edx, %eax
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; FASTINCDEC-NEXT: retq
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;
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; SLOWINCDEC-LABEL: test_sub_1_cmov_sgt:
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; SLOWINCDEC: # %bb.0: # %entry
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; SLOWINCDEC-NEXT: movl %esi, %eax
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; SLOWINCDEC-NEXT: lock addq $-1, (%rdi)
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; SLOWINCDEC-NEXT: cmovll %edx, %eax
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; SLOWINCDEC-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
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%tmp1 = icmp sgt i64 %tmp0, 0
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%tmp2 = select i1 %tmp1, i32 %a0, i32 %a1
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ret i32 %tmp2
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}
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; FIXME: (setcc slt x, 0) gets combined into shr early.
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define i8 @test_add_1_setcc_slt(i64* %p) #0 {
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; CHECK-LABEL: test_add_1_setcc_slt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: shrq $63, %rax
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; CHECK-NEXT: # kill: def $al killed $al killed $rax
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
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%tmp1 = icmp slt i64 %tmp0, 0
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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define i8 @test_sub_1_setcc_sgt(i64* %p) #0 {
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; FASTINCDEC-LABEL: test_sub_1_setcc_sgt:
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; FASTINCDEC: # %bb.0: # %entry
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; FASTINCDEC-NEXT: lock decq (%rdi)
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; FASTINCDEC-NEXT: setge %al
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; FASTINCDEC-NEXT: retq
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;
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; SLOWINCDEC-LABEL: test_sub_1_setcc_sgt:
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; SLOWINCDEC: # %bb.0: # %entry
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; SLOWINCDEC-NEXT: lock addq $-1, (%rdi)
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; SLOWINCDEC-NEXT: setge %al
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; SLOWINCDEC-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
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%tmp1 = icmp sgt i64 %tmp0, 0
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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define i32 @test_add_1_brcond_sge(i64* %p, i32 %a0, i32 %a1) #0 {
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; FASTINCDEC-LABEL: test_add_1_brcond_sge:
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; FASTINCDEC: # %bb.0: # %entry
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; FASTINCDEC-NEXT: lock incq (%rdi)
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; FASTINCDEC-NEXT: jle .LBB6_2
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; FASTINCDEC-NEXT: # %bb.1: # %t
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; FASTINCDEC-NEXT: movl %esi, %eax
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; FASTINCDEC-NEXT: retq
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; FASTINCDEC-NEXT: .LBB6_2: # %f
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; FASTINCDEC-NEXT: movl %edx, %eax
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; FASTINCDEC-NEXT: retq
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;
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; SLOWINCDEC-LABEL: test_add_1_brcond_sge:
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; SLOWINCDEC: # %bb.0: # %entry
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; SLOWINCDEC-NEXT: lock addq $1, (%rdi)
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; SLOWINCDEC-NEXT: jle .LBB6_2
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; SLOWINCDEC-NEXT: # %bb.1: # %t
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; SLOWINCDEC-NEXT: movl %esi, %eax
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; SLOWINCDEC-NEXT: retq
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; SLOWINCDEC-NEXT: .LBB6_2: # %f
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; SLOWINCDEC-NEXT: movl %edx, %eax
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; SLOWINCDEC-NEXT: retq
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entry:
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%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
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%tmp1 = icmp sge i64 %tmp0, 0
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br i1 %tmp1, label %t, label %f
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t:
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ret i32 %a0
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f:
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ret i32 %a1
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}
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; Also make sure we don't muck with condition codes that we should ignore.
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; No need to test unsigned comparisons, as they should all be simplified.
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define i32 @test_add_1_cmov_sle(i64* %p, i32 %a0, i32 %a1) #0 {
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; CHECK-LABEL: test_add_1_cmov_sle:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: lock xaddq %rcx, (%rdi)
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; CHECK-NEXT: testq %rcx, %rcx
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; CHECK-NEXT: cmovgl %edx, %eax
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
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%tmp1 = icmp sle i64 %tmp0, 0
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%tmp2 = select i1 %tmp1, i32 %a0, i32 %a1
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ret i32 %tmp2
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}
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define i32 @test_add_1_cmov_sgt(i64* %p, i32 %a0, i32 %a1) #0 {
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; CHECK-LABEL: test_add_1_cmov_sgt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: lock xaddq %rcx, (%rdi)
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; CHECK-NEXT: testq %rcx, %rcx
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; CHECK-NEXT: cmovlel %edx, %eax
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
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%tmp1 = icmp sgt i64 %tmp0, 0
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%tmp2 = select i1 %tmp1, i32 %a0, i32 %a1
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ret i32 %tmp2
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}
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; Test a result being used by more than just the comparison.
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define i8 @test_add_1_setcc_sgt_reuse(i64* %p, i64* %p2) #0 {
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; CHECK-LABEL: test_add_1_setcc_sgt_reuse:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl $1, %ecx
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; CHECK-NEXT: lock xaddq %rcx, (%rdi)
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; CHECK-NEXT: testq %rcx, %rcx
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; CHECK-NEXT: setg %al
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; CHECK-NEXT: movq %rcx, (%rsi)
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw add i64* %p, i64 1 seq_cst
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%tmp1 = icmp sgt i64 %tmp0, 0
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%tmp2 = zext i1 %tmp1 to i8
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store i64 %tmp0, i64* %p2
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ret i8 %tmp2
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}
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define i8 @test_sub_2_setcc_sgt(i64* %p) #0 {
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; CHECK-LABEL: test_sub_2_setcc_sgt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq $-2, %rax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: testq %rax, %rax
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; CHECK-NEXT: setg %al
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 2 seq_cst
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%tmp1 = icmp sgt i64 %tmp0, 0
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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; TODO: It's possible to use "lock inc" here, but both cmovs need to be updated.
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define i8 @test_add_1_cmov_cmov(i64* %p, i8* %q) #0 {
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; CHECK-LABEL: test_add_1_cmov_cmov:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: lock xaddq %rax, (%rdi)
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; CHECK-NEXT: testq %rax, %rax
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; CHECK-NEXT: movl $12, %eax
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; CHECK-NEXT: movl $34, %ecx
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; CHECK-NEXT: cmovsl %eax, %ecx
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; CHECK-NEXT: movb %cl, (%rsi)
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; CHECK-NEXT: movl $56, %ecx
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; CHECK-NEXT: movl $78, %eax
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; CHECK-NEXT: cmovsl %ecx, %eax
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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entry:
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%add = atomicrmw add i64* %p, i64 1 seq_cst
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%cmp = icmp slt i64 %add, 0
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%s1 = select i1 %cmp, i8 12, i8 34
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store i8 %s1, i8* %q
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%s2 = select i1 %cmp, i8 56, i8 78
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ret i8 %s2
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}
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define i8 @test_sub_1_cmp_1_setcc_eq(i64* %p) #0 {
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; FASTINCDEC-LABEL: test_sub_1_cmp_1_setcc_eq:
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; FASTINCDEC: # %bb.0: # %entry
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; FASTINCDEC-NEXT: lock decq (%rdi)
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; FASTINCDEC-NEXT: sete %al
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; FASTINCDEC-NEXT: retq
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;
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; SLOWINCDEC-LABEL: test_sub_1_cmp_1_setcc_eq:
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; SLOWINCDEC: # %bb.0: # %entry
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; SLOWINCDEC-NEXT: lock subq $1, (%rdi)
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; SLOWINCDEC-NEXT: sete %al
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; SLOWINCDEC-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
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%tmp1 = icmp eq i64 %tmp0, 1
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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define i8 @test_sub_1_cmp_1_setcc_ne(i64* %p) #0 {
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; FASTINCDEC-LABEL: test_sub_1_cmp_1_setcc_ne:
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; FASTINCDEC: # %bb.0: # %entry
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; FASTINCDEC-NEXT: lock decq (%rdi)
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; FASTINCDEC-NEXT: setne %al
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; FASTINCDEC-NEXT: retq
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;
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; SLOWINCDEC-LABEL: test_sub_1_cmp_1_setcc_ne:
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; SLOWINCDEC: # %bb.0: # %entry
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; SLOWINCDEC-NEXT: lock subq $1, (%rdi)
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; SLOWINCDEC-NEXT: setne %al
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; SLOWINCDEC-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
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%tmp1 = icmp ne i64 %tmp0, 1
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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define i8 @test_sub_1_cmp_1_setcc_ugt(i64* %p) #0 {
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; CHECK-LABEL: test_sub_1_cmp_1_setcc_ugt:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lock subq $1, (%rdi)
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; CHECK-NEXT: seta %al
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
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%tmp1 = icmp ugt i64 %tmp0, 1
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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define i8 @test_sub_1_cmp_1_setcc_sle(i64* %p) #0 {
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; FASTINCDEC-LABEL: test_sub_1_cmp_1_setcc_sle:
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; FASTINCDEC: # %bb.0: # %entry
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; FASTINCDEC-NEXT: lock decq (%rdi)
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; FASTINCDEC-NEXT: setle %al
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; FASTINCDEC-NEXT: retq
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;
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; SLOWINCDEC-LABEL: test_sub_1_cmp_1_setcc_sle:
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; SLOWINCDEC: # %bb.0: # %entry
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; SLOWINCDEC-NEXT: lock subq $1, (%rdi)
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; SLOWINCDEC-NEXT: setle %al
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; SLOWINCDEC-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 1 seq_cst
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%tmp1 = icmp sle i64 %tmp0, 1
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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define i8 @test_sub_3_cmp_3_setcc_eq(i64* %p) #0 {
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; CHECK-LABEL: test_sub_3_cmp_3_setcc_eq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lock subq $3, (%rdi)
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; CHECK-NEXT: sete %al
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 3 seq_cst
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%tmp1 = icmp eq i64 %tmp0, 3
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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define i8 @test_sub_3_cmp_3_setcc_uge(i64* %p) #0 {
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; CHECK-LABEL: test_sub_3_cmp_3_setcc_uge:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lock subq $3, (%rdi)
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; CHECK-NEXT: setae %al
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; CHECK-NEXT: retq
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entry:
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%tmp0 = atomicrmw sub i64* %p, i64 3 seq_cst
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%tmp1 = icmp uge i64 %tmp0, 3
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%tmp2 = zext i1 %tmp1 to i8
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ret i8 %tmp2
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}
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attributes #0 = { nounwind }
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