0aef747b84
The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
295 lines
8.9 KiB
LLVM
295 lines
8.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+cmov -mtriple=i386-pc-linux -verify-machineinstrs < %s | FileCheck %s -check-prefix=LINUX
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; RUN: llc -mattr=+cmov -mtriple=i386-macosx -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s -check-prefix=PIC
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@sc64 = external dso_local global i64
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define i64 @atomic_max_i64() nounwind {
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; LINUX-LABEL: atomic_max_i64:
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; LINUX: # %bb.0: # %entry
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; LINUX-NEXT: pushl %ebx
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; LINUX-NEXT: pushl %esi
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; LINUX-NEXT: movl sc64+4, %edx
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; LINUX-NEXT: movl sc64, %eax
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; LINUX-NEXT: movl $5, %esi
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; LINUX-NEXT: .p2align 4, 0x90
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; LINUX-NEXT: .LBB0_1: # %atomicrmw.start
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; LINUX-NEXT: # =>This Inner Loop Header: Depth=1
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; LINUX-NEXT: cmpl %eax, %esi
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; LINUX-NEXT: movl $0, %ecx
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; LINUX-NEXT: sbbl %edx, %ecx
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; LINUX-NEXT: movl $0, %ecx
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; LINUX-NEXT: cmovll %edx, %ecx
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; LINUX-NEXT: movl $5, %ebx
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; LINUX-NEXT: cmovll %eax, %ebx
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; LINUX-NEXT: lock cmpxchg8b sc64
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; LINUX-NEXT: jne .LBB0_1
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; LINUX-NEXT: # %bb.2: # %atomicrmw.end
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; LINUX-NEXT: popl %esi
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; LINUX-NEXT: popl %ebx
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; LINUX-NEXT: retl
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;
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; PIC-LABEL: atomic_max_i64:
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; PIC: ## %bb.0: ## %entry
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; PIC-NEXT: pushl %ebx
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; PIC-NEXT: pushl %edi
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; PIC-NEXT: pushl %esi
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; PIC-NEXT: calll L0$pb
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; PIC-NEXT: L0$pb:
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; PIC-NEXT: popl %eax
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; PIC-NEXT: movl L_sc64$non_lazy_ptr-L0$pb(%eax), %esi
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; PIC-NEXT: movl (%esi), %eax
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; PIC-NEXT: movl 4(%esi), %edx
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; PIC-NEXT: movl $5, %edi
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; PIC-NEXT: .p2align 4, 0x90
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; PIC-NEXT: LBB0_1: ## %atomicrmw.start
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; PIC-NEXT: ## =>This Inner Loop Header: Depth=1
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; PIC-NEXT: cmpl %eax, %edi
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; PIC-NEXT: movl $0, %ecx
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; PIC-NEXT: sbbl %edx, %ecx
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; PIC-NEXT: movl $0, %ecx
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; PIC-NEXT: cmovll %edx, %ecx
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; PIC-NEXT: movl $5, %ebx
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; PIC-NEXT: cmovll %eax, %ebx
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; PIC-NEXT: lock cmpxchg8b (%esi)
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; PIC-NEXT: jne LBB0_1
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; PIC-NEXT: ## %bb.2: ## %atomicrmw.end
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; PIC-NEXT: popl %esi
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; PIC-NEXT: popl %edi
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; PIC-NEXT: popl %ebx
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; PIC-NEXT: retl
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entry:
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%max = atomicrmw max i64* @sc64, i64 5 acquire
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ret i64 %max
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}
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define i64 @atomic_min_i64() nounwind {
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; LINUX-LABEL: atomic_min_i64:
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; LINUX: # %bb.0: # %entry
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; LINUX-NEXT: pushl %ebx
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; LINUX-NEXT: movl sc64+4, %edx
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; LINUX-NEXT: movl sc64, %eax
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; LINUX-NEXT: .p2align 4, 0x90
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; LINUX-NEXT: .LBB1_1: # %atomicrmw.start
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; LINUX-NEXT: # =>This Inner Loop Header: Depth=1
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; LINUX-NEXT: cmpl $7, %eax
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; LINUX-NEXT: movl %edx, %ecx
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; LINUX-NEXT: sbbl $0, %ecx
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; LINUX-NEXT: movl $0, %ecx
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; LINUX-NEXT: cmovll %edx, %ecx
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; LINUX-NEXT: movl $6, %ebx
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; LINUX-NEXT: cmovll %eax, %ebx
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; LINUX-NEXT: lock cmpxchg8b sc64
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; LINUX-NEXT: jne .LBB1_1
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; LINUX-NEXT: # %bb.2: # %atomicrmw.end
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; LINUX-NEXT: popl %ebx
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; LINUX-NEXT: retl
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;
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; PIC-LABEL: atomic_min_i64:
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; PIC: ## %bb.0: ## %entry
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; PIC-NEXT: pushl %ebx
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; PIC-NEXT: pushl %esi
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; PIC-NEXT: calll L1$pb
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; PIC-NEXT: L1$pb:
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; PIC-NEXT: popl %eax
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; PIC-NEXT: movl L_sc64$non_lazy_ptr-L1$pb(%eax), %esi
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; PIC-NEXT: movl (%esi), %eax
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; PIC-NEXT: movl 4(%esi), %edx
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; PIC-NEXT: .p2align 4, 0x90
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; PIC-NEXT: LBB1_1: ## %atomicrmw.start
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; PIC-NEXT: ## =>This Inner Loop Header: Depth=1
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; PIC-NEXT: cmpl $7, %eax
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; PIC-NEXT: movl %edx, %ecx
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; PIC-NEXT: sbbl $0, %ecx
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; PIC-NEXT: movl $0, %ecx
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; PIC-NEXT: cmovll %edx, %ecx
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; PIC-NEXT: movl $6, %ebx
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; PIC-NEXT: cmovll %eax, %ebx
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; PIC-NEXT: lock cmpxchg8b (%esi)
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; PIC-NEXT: jne LBB1_1
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; PIC-NEXT: ## %bb.2: ## %atomicrmw.end
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; PIC-NEXT: popl %esi
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; PIC-NEXT: popl %ebx
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; PIC-NEXT: retl
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entry:
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%min = atomicrmw min i64* @sc64, i64 6 acquire
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ret i64 %min
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}
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define i64 @atomic_umax_i64() nounwind {
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; LINUX-LABEL: atomic_umax_i64:
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; LINUX: # %bb.0: # %entry
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; LINUX-NEXT: pushl %ebx
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; LINUX-NEXT: pushl %esi
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; LINUX-NEXT: movl sc64+4, %edx
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; LINUX-NEXT: movl sc64, %eax
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; LINUX-NEXT: movl $7, %esi
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; LINUX-NEXT: .p2align 4, 0x90
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; LINUX-NEXT: .LBB2_1: # %atomicrmw.start
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; LINUX-NEXT: # =>This Inner Loop Header: Depth=1
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; LINUX-NEXT: cmpl %eax, %esi
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; LINUX-NEXT: movl $0, %ecx
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; LINUX-NEXT: sbbl %edx, %ecx
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; LINUX-NEXT: movl $0, %ecx
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; LINUX-NEXT: cmovbl %edx, %ecx
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; LINUX-NEXT: movl $7, %ebx
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; LINUX-NEXT: cmovbl %eax, %ebx
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; LINUX-NEXT: lock cmpxchg8b sc64
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; LINUX-NEXT: jne .LBB2_1
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; LINUX-NEXT: # %bb.2: # %atomicrmw.end
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; LINUX-NEXT: popl %esi
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; LINUX-NEXT: popl %ebx
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; LINUX-NEXT: retl
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;
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; PIC-LABEL: atomic_umax_i64:
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; PIC: ## %bb.0: ## %entry
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; PIC-NEXT: pushl %ebx
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; PIC-NEXT: pushl %edi
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; PIC-NEXT: pushl %esi
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; PIC-NEXT: calll L2$pb
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; PIC-NEXT: L2$pb:
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; PIC-NEXT: popl %eax
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; PIC-NEXT: movl L_sc64$non_lazy_ptr-L2$pb(%eax), %esi
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; PIC-NEXT: movl (%esi), %eax
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; PIC-NEXT: movl 4(%esi), %edx
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; PIC-NEXT: movl $7, %edi
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; PIC-NEXT: .p2align 4, 0x90
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; PIC-NEXT: LBB2_1: ## %atomicrmw.start
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; PIC-NEXT: ## =>This Inner Loop Header: Depth=1
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; PIC-NEXT: cmpl %eax, %edi
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; PIC-NEXT: movl $0, %ecx
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; PIC-NEXT: sbbl %edx, %ecx
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; PIC-NEXT: movl $0, %ecx
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; PIC-NEXT: cmovbl %edx, %ecx
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; PIC-NEXT: movl $7, %ebx
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; PIC-NEXT: cmovbl %eax, %ebx
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; PIC-NEXT: lock cmpxchg8b (%esi)
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; PIC-NEXT: jne LBB2_1
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; PIC-NEXT: ## %bb.2: ## %atomicrmw.end
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; PIC-NEXT: popl %esi
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; PIC-NEXT: popl %edi
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; PIC-NEXT: popl %ebx
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; PIC-NEXT: retl
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entry:
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%umax = atomicrmw umax i64* @sc64, i64 7 acquire
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ret i64 %umax
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}
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define i64 @atomic_umin_i64() nounwind {
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; LINUX-LABEL: atomic_umin_i64:
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; LINUX: # %bb.0: # %entry
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; LINUX-NEXT: pushl %ebx
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; LINUX-NEXT: movl sc64+4, %edx
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; LINUX-NEXT: movl sc64, %eax
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; LINUX-NEXT: .p2align 4, 0x90
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; LINUX-NEXT: .LBB3_1: # %atomicrmw.start
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; LINUX-NEXT: # =>This Inner Loop Header: Depth=1
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; LINUX-NEXT: cmpl $9, %eax
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; LINUX-NEXT: movl %edx, %ecx
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; LINUX-NEXT: sbbl $0, %ecx
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; LINUX-NEXT: movl $0, %ecx
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; LINUX-NEXT: cmovbl %edx, %ecx
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; LINUX-NEXT: movl $8, %ebx
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; LINUX-NEXT: cmovbl %eax, %ebx
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; LINUX-NEXT: lock cmpxchg8b sc64
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; LINUX-NEXT: jne .LBB3_1
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; LINUX-NEXT: # %bb.2: # %atomicrmw.end
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; LINUX-NEXT: popl %ebx
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; LINUX-NEXT: retl
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;
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; PIC-LABEL: atomic_umin_i64:
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; PIC: ## %bb.0: ## %entry
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; PIC-NEXT: pushl %ebx
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; PIC-NEXT: pushl %esi
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; PIC-NEXT: calll L3$pb
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; PIC-NEXT: L3$pb:
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; PIC-NEXT: popl %eax
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; PIC-NEXT: movl L_sc64$non_lazy_ptr-L3$pb(%eax), %esi
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; PIC-NEXT: movl (%esi), %eax
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; PIC-NEXT: movl 4(%esi), %edx
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; PIC-NEXT: .p2align 4, 0x90
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; PIC-NEXT: LBB3_1: ## %atomicrmw.start
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; PIC-NEXT: ## =>This Inner Loop Header: Depth=1
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; PIC-NEXT: cmpl $9, %eax
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; PIC-NEXT: movl %edx, %ecx
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; PIC-NEXT: sbbl $0, %ecx
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; PIC-NEXT: movl $0, %ecx
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; PIC-NEXT: cmovbl %edx, %ecx
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; PIC-NEXT: movl $8, %ebx
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; PIC-NEXT: cmovbl %eax, %ebx
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; PIC-NEXT: lock cmpxchg8b (%esi)
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; PIC-NEXT: jne LBB3_1
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; PIC-NEXT: ## %bb.2: ## %atomicrmw.end
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; PIC-NEXT: popl %esi
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; PIC-NEXT: popl %ebx
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; PIC-NEXT: retl
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entry:
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%umin = atomicrmw umin i64* @sc64, i64 8 acquire
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ret i64 %umin
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}
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@id = internal global i64 0, align 8
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define void @tf_bug(i8* %ptr) nounwind {
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; LINUX-LABEL: tf_bug:
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; LINUX: # %bb.0: # %entry
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; LINUX-NEXT: pushl %ebx
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; LINUX-NEXT: pushl %esi
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; LINUX-NEXT: movl {{[0-9]+}}(%esp), %esi
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; LINUX-NEXT: movl id+4, %edx
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; LINUX-NEXT: movl id, %eax
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; LINUX-NEXT: .p2align 4, 0x90
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; LINUX-NEXT: .LBB4_1: # %atomicrmw.start
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; LINUX-NEXT: # =>This Inner Loop Header: Depth=1
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; LINUX-NEXT: movl %eax, %ebx
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; LINUX-NEXT: addl $1, %ebx
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; LINUX-NEXT: movl %edx, %ecx
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; LINUX-NEXT: adcl $0, %ecx
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; LINUX-NEXT: lock cmpxchg8b id
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; LINUX-NEXT: jne .LBB4_1
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; LINUX-NEXT: # %bb.2: # %atomicrmw.end
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; LINUX-NEXT: addl $1, %eax
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; LINUX-NEXT: adcl $0, %edx
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; LINUX-NEXT: movl %eax, (%esi)
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; LINUX-NEXT: movl %edx, 4(%esi)
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; LINUX-NEXT: popl %esi
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; LINUX-NEXT: popl %ebx
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; LINUX-NEXT: retl
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;
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; PIC-LABEL: tf_bug:
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; PIC: ## %bb.0: ## %entry
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; PIC-NEXT: pushl %ebx
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; PIC-NEXT: pushl %edi
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; PIC-NEXT: pushl %esi
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; PIC-NEXT: calll L4$pb
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; PIC-NEXT: L4$pb:
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; PIC-NEXT: popl %edi
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; PIC-NEXT: movl {{[0-9]+}}(%esp), %esi
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; PIC-NEXT: movl (_id-L4$pb)+4(%edi), %edx
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; PIC-NEXT: movl _id-L4$pb(%edi), %eax
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; PIC-NEXT: .p2align 4, 0x90
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; PIC-NEXT: LBB4_1: ## %atomicrmw.start
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; PIC-NEXT: ## =>This Inner Loop Header: Depth=1
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; PIC-NEXT: movl %eax, %ebx
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; PIC-NEXT: addl $1, %ebx
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; PIC-NEXT: movl %edx, %ecx
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; PIC-NEXT: adcl $0, %ecx
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; PIC-NEXT: lock cmpxchg8b _id-L4$pb(%edi)
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; PIC-NEXT: jne LBB4_1
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; PIC-NEXT: ## %bb.2: ## %atomicrmw.end
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; PIC-NEXT: addl $1, %eax
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; PIC-NEXT: adcl $0, %edx
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; PIC-NEXT: movl %eax, (%esi)
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; PIC-NEXT: movl %edx, 4(%esi)
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; PIC-NEXT: popl %esi
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; PIC-NEXT: popl %edi
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; PIC-NEXT: popl %ebx
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; PIC-NEXT: retl
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entry:
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%tmp1 = atomicrmw add i64* @id, i64 1 seq_cst
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%tmp2 = add i64 %tmp1, 1
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%tmp3 = bitcast i8* %ptr to i64*
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store i64 %tmp2, i64* %tmp3, align 4
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ret void
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}
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