0aef747b84
The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
155 lines
5.6 KiB
LLVM
155 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX
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declare i32 @llvm.uadd.sat.i32 (i32, i32)
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declare i64 @llvm.uadd.sat.i64 (i64, i64)
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declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
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; fold (uadd_sat x, undef) -> -1
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define i32 @combine_undef_i32(i32 %a0) {
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; CHECK-LABEL: combine_undef_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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%res = call i32 @llvm.uadd.sat.i32(i32 %a0, i32 undef)
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ret i32 %res
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}
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define <8 x i16> @combine_undef_v8i16(<8 x i16> %a0) {
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; SSE-LABEL: combine_undef_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_undef_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%res = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> undef, <8 x i16> %a0)
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ret <8 x i16> %res
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}
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; fold (uadd_sat c1, c2) -> c3
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define i32 @combine_constfold_i32() {
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; CHECK-LABEL: combine_constfold_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: retq
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%res = call i32 @llvm.uadd.sat.i32(i32 4294967295, i32 100)
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ret i32 %res
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}
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define <8 x i16> @combine_constfold_v8i16() {
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; SSE-LABEL: combine_constfold_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps {{.*#+}} xmm0 = [1,65535,256,65535,65535,65535,2,65535]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_constfold_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1,65535,256,65535,65535,65535,2,65535]
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; AVX-NEXT: retq
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%res = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> <i16 0, i16 1, i16 255, i16 65535, i16 -1, i16 -255, i16 -65535, i16 1>, <8 x i16> <i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535>)
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ret <8 x i16> %res
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}
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define <8 x i16> @combine_constfold_undef_v8i16() {
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; SSE-LABEL: combine_constfold_undef_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65535,65535,65535,65535,65535,2,65535]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_constfold_undef_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [65535,65535,65535,65535,65535,65535,2,65535]
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; AVX-NEXT: retq
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%res = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> <i16 undef, i16 1, i16 undef, i16 65535, i16 -1, i16 -255, i16 -65535, i16 1>, <8 x i16> <i16 1, i16 undef, i16 undef, i16 65535, i16 1, i16 65535, i16 1, i16 65535>)
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ret <8 x i16> %res
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}
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; fold (uadd_sat c, x) -> (add_ssat x, c)
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define i32 @combine_constant_i32(i32 %a0) {
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; CHECK-LABEL: combine_constant_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: incl %edi
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovnel %edi, %eax
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; CHECK-NEXT: retq
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%1 = call i32 @llvm.uadd.sat.i32(i32 1, i32 %a0)
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ret i32 %1
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}
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define <8 x i16> @combine_constant_v8i16(<8 x i16> %a0) {
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; SSE-LABEL: combine_constant_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: paddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_constant_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vpaddusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16> %a0)
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ret <8 x i16> %1
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}
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; fold (uadd_sat c, 0) -> x
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define i32 @combine_zero_i32(i32 %a0) {
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; CHECK-LABEL: combine_zero_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%1 = call i32 @llvm.uadd.sat.i32(i32 %a0, i32 0)
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ret i32 %1
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}
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define <8 x i16> @combine_zero_v8i16(<8 x i16> %a0) {
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; CHECK-LABEL: combine_zero_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %a0, <8 x i16> zeroinitializer)
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ret <8 x i16> %1
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}
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; fold (uadd_sat x, y) -> (add x, y) iff no overflow
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define i32 @combine_no_overflow_i32(i32 %a0, i32 %a1) {
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; CHECK-LABEL: combine_no_overflow_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: shrl $16, %edi
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; CHECK-NEXT: shrl $16, %esi
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; CHECK-NEXT: leal (%rsi,%rdi), %eax
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; CHECK-NEXT: retq
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%1 = lshr i32 %a0, 16
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%2 = lshr i32 %a1, 16
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%3 = call i32 @llvm.uadd.sat.i32(i32 %1, i32 %2)
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ret i32 %3
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}
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define <8 x i16> @combine_no_overflow_v8i16(<8 x i16> %a0, <8 x i16> %a1) {
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; SSE-LABEL: combine_no_overflow_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: psrlw $10, %xmm0
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; SSE-NEXT: psrlw $10, %xmm1
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; SSE-NEXT: paddw %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_no_overflow_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsrlw $10, %xmm0, %xmm0
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; AVX-NEXT: vpsrlw $10, %xmm1, %xmm1
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; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = lshr <8 x i16> %a0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
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%2 = lshr <8 x i16> %a1, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
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%3 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %1, <8 x i16> %2)
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ret <8 x i16> %3
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}
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