0aef747b84
The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
143 lines
4.6 KiB
LLVM
143 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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;
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; NOTE: this is generated by utils/update_llc_test_checks.py but we can't check NAN types (PR30443),
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; so we need to edit it to remove the NAN constant comments
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;
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; fabs(c1) -> c2
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define float @combine_fabs_constant() {
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; SSE-LABEL: combine_fabs_constant:
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; SSE: # %bb.0:
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; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_fabs_constant:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: retq
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%1 = call float @llvm.fabs.f32(float -2.0)
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ret float %1
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}
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define <4 x float> @combine_vec_fabs_constant() {
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; SSE-LABEL: combine_vec_fabs_constant:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps {{.*#+}} xmm0 = [0.0E+0,0.0E+0,2.0E+0,2.0E+0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fabs_constant:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [0.0E+0,0.0E+0,2.0E+0,2.0E+0]
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> <float 0.0, float -0.0, float 2.0, float -2.0>)
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ret <4 x float> %1
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}
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; fabs(fabs(x)) -> fabs(x)
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define float @combine_fabs_fabs(float %a) {
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; SSE-LABEL: combine_fabs_fabs:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_fabs_fabs:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call float @llvm.fabs.f32(float %a)
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%2 = call float @llvm.fabs.f32(float %1)
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ret float %2
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}
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define <4 x float> @combine_vec_fabs_fabs(<4 x float> %a) {
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; SSE-LABEL: combine_vec_fabs_fabs:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fabs_fabs:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
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%2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %1)
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ret <4 x float> %2
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}
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; fabs(fneg(x)) -> fabs(x)
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define float @combine_fabs_fneg(float %a) {
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; SSE-LABEL: combine_fabs_fneg:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_fabs_fneg:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = fsub float -0.0, %a
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%2 = call float @llvm.fabs.f32(float %1)
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ret float %2
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}
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define <4 x float> @combine_vec_fabs_fneg(<4 x float> %a) {
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; SSE-LABEL: combine_vec_fabs_fneg:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fabs_fneg:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %a
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%2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %1)
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ret <4 x float> %2
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}
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; fabs(fcopysign(x, y)) -> fabs(x)
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define float @combine_fabs_fcopysign(float %a, float %b) {
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; SSE-LABEL: combine_fabs_fcopysign:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_fabs_fcopysign:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call float @llvm.copysign.f32(float %a, float %b)
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%2 = call float @llvm.fabs.f32(float %1)
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ret float %2
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}
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define <4 x float> @combine_vec_fabs_fcopysign(<4 x float> %a, <4 x float> %b) {
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; SSE-LABEL: combine_vec_fabs_fcopysign:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_fabs_fcopysign:
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; AVX: # %bb.0:
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; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b)
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%2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %1)
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ret <4 x float> %2
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}
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declare float @llvm.fabs.f32(float %p)
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declare float @llvm.copysign.f32(float %Mag, float %Sgn)
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declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
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declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)
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