Files
clang-p2996/llvm/test/CodeGen/X86/legalize-shift.ll
Sanjay Patel c2592c374e [SDAG] simplify bitwise logic with repeated operand
We do not have general reassociation here (and probably
do not need it), but I noticed these were missing in
patches/tests motivated by D111530, so we can at
least handle the simplest patterns.

The VE test diff looks correct, but we miss that
pattern in IR currently:
https://alive2.llvm.org/ce/z/u66_PM
2022-03-13 11:12:30 -04:00

23 lines
643 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
define void @PR36250() nounwind {
; X86-LABEL: PR36250:
; X86: # %bb.0:
; X86-NEXT: cmpl $0, (%eax)
; X86-NEXT: sete (%eax)
; X86-NEXT: retl
;
; X64-LABEL: PR36250:
; X64: # %bb.0:
; X64-NEXT: cmpq $0, (%rax)
; X64-NEXT: sete (%rax)
; X64-NEXT: retq
%1 = load i448, i448* undef
%2 = sub i448 0, %1
%3 = icmp eq i448 %1, %2
store i1 %3, i1* undef
ret void
}