016f42e3dc
lrint/llrint are defined as rounding using the current rounding mode. Numbers that can't be converted raise FE_INVALID and an implementation defined value is returned. They may also write to errno. I believe this means we can use cvtss2si/cvtsd2si or fist to convert as long as -fno-math-errno is passed on the command line. Clang will leave them as libcalls if errno is enabled so they won't become ISD::LRINT/LLRINT in SelectionDAG. For 64-bit results on a 32-bit target we can't use cvtss2si/cvtsd2si but we can use fist since it can write to a 64-bit memory location. Though maybe we could consider using vcvtps2qq/vcvtpd2qq on avx512dq targets? gcc also does this optimization. I think we might be able to do this with STRICT_LRINT/LLRINT as well, but I've left that for future work. Differential Revision: https://reviews.llvm.org/D73859
51 lines
1.5 KiB
LLVM
51 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=CHECK,AVX
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define i64 @testmsxs(float %x) {
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; SSE-LABEL: testmsxs:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: cvtss2si %xmm0, %rax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: testmsxs:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtss2si %xmm0, %rax
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; AVX-NEXT: retq
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
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ret i64 %0
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}
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define i64 @testmsxd(double %x) {
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; SSE-LABEL: testmsxd:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: cvtsd2si %xmm0, %rax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: testmsxd:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vcvtsd2si %xmm0, %rax
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; AVX-NEXT: retq
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
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ret i64 %0
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}
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define i64 @testmsll(x86_fp80 %x) {
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; CHECK-LABEL: testmsll:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fistpll -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
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; CHECK-NEXT: retq
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entry:
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%0 = tail call i64 @llvm.lrint.i64.f80(x86_fp80 %x)
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ret i64 %0
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}
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declare i64 @llvm.lrint.i64.f32(float) nounwind readnone
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declare i64 @llvm.lrint.i64.f64(double) nounwind readnone
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declare i64 @llvm.lrint.i64.f80(x86_fp80) nounwind readnone
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