d510fd2bed
combineMulToPMADDWD is currently limited to legal types, but there's no reason why we can't handle any larger type that the existing SplitOpsAndApply code can use to split to legal X86ISD::VPMADDWD ops. This also exposed a missed opportunity for pre-SSE41 targets to handle SEXT ops from types smaller than vXi16 - without PMOVSX instructions these will always be expanded to unpack+shifts, so we can cheat and convert this into a ZEXT(SEXT()) sequence to make it a valid PMADDWD op. Differential Revision: https://reviews.llvm.org/D110995
58 lines
2.9 KiB
LLVM
58 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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; A combine forming X86ISD::VSHLI was missing a test and not using
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; TargetConstant for the RHS operand.
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; https://bugs.chromium.org/p/chromium/issues/detail?id=1005750
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define <8 x i8> @vshli_target_constant(<8 x i16> %arg, <8 x i32> %arg1) {
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; CHECK-LABEL: vshli_target_constant:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [2863311531,2863311531,2863311531,2863311531]
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; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
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; CHECK-NEXT: pmuludq %xmm0, %xmm1
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
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; CHECK-NEXT: pmuludq %xmm0, %xmm3
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; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,3,2,3]
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; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
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; CHECK-NEXT: psrld $1, %xmm1
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; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
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; CHECK-NEXT: pmuludq %xmm0, %xmm2
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; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
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; CHECK-NEXT: pmuludq %xmm0, %xmm3
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,3,2,3]
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; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
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; CHECK-NEXT: psrld $1, %xmm2
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; CHECK-NEXT: movdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
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; CHECK-NEXT: pand %xmm3, %xmm2
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; CHECK-NEXT: pand %xmm3, %xmm1
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; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: pxor %xmm4, %xmm4
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; CHECK-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
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; CHECK-NEXT: movdqa %xmm0, %xmm5
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; CHECK-NEXT: punpckhwd {{.*#+}} xmm5 = xmm5[4],xmm4[4],xmm5[5],xmm4[5],xmm5[6],xmm4[6],xmm5[7],xmm4[7]
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; CHECK-NEXT: pmaddwd %xmm2, %xmm5
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; CHECK-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
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; CHECK-NEXT: pmaddwd %xmm1, %xmm0
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [128,128,128,128]
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; CHECK-NEXT: paddd %xmm1, %xmm5
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; CHECK-NEXT: paddd %xmm1, %xmm0
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; CHECK-NEXT: psrld $8, %xmm0
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; CHECK-NEXT: psrld $8, %xmm5
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; CHECK-NEXT: pand %xmm3, %xmm5
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; CHECK-NEXT: pand %xmm3, %xmm0
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; CHECK-NEXT: packuswb %xmm5, %xmm0
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; CHECK-NEXT: packuswb %xmm0, %xmm0
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; CHECK-NEXT: retq
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bb:
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%tmp = udiv <8 x i32> %arg1, <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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%tmp2 = and <8 x i32> %tmp, <i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255, i32 255>
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%tmp3 = load <8 x i8>, <8 x i8>* undef, align 1
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%tmp4 = zext <8 x i8> %tmp3 to <8 x i32>
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%tmp5 = mul nuw nsw <8 x i32> %tmp2, %tmp4
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%tmp6 = add nuw nsw <8 x i32> %tmp5, <i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128, i32 128>
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%tmp7 = lshr <8 x i32> %tmp6, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
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%tmp8 = trunc <8 x i32> %tmp7 to <8 x i8>
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ret <8 x i8> %tmp8
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}
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