f7d4cafe5a
This patch supports R_RISCV_SET* and R_RISCV_32_PCREL relocations in JITLink. Reviewed By: StephenFan Differential Revision: https://reviews.llvm.org/D117082
32 lines
911 B
ArmAsm
32 lines
911 B
ArmAsm
# RUN: rm -rf %t && mkdir -p %t
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# RUN: llvm-mc -triple=riscv64 -filetype=obj -o %t/riscv64_reloc_set.o %s
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# RUN: llvm-mc -triple=riscv32 -filetype=obj -o %t/riscv32_reloc_set.o %s
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# RUN: llvm-jitlink -noexec \
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# RUN: -slab-allocate 100Kb -slab-address 0xfff0f0f0 -slab-page-size 4096 \
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# RUN: -check %s %t/riscv64_reloc_set.o
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# RUN: llvm-jitlink -noexec \
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# RUN: -slab-allocate 100Kb -slab-address 0xfff0f0f0 -slab-page-size 4096 \
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# RUN: -check %s %t/riscv32_reloc_set.o
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# jitlink-check: *{4}(foo) = foo
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# jitlink-check: *{2}(foo+4) = foo[15:0]
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# jitlink-check: *{1}(foo+6) = foo[7:0]
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# jitlink-check: *{1}(foo+7) = foo[5:0]
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.global main
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main:
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lw a0, foo
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.section ".rodata","",@progbits
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.type foo,@object
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foo:
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.reloc foo, R_RISCV_SET32, foo
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.reloc foo+4, R_RISCV_SET16, foo
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.reloc foo+6, R_RISCV_SET8, foo
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.reloc foo+7, R_RISCV_SET6, foo
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.word 0
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.half 0
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.byte 0
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.byte 0
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.size foo, 8
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