b0a0df9809
If the alternate cmp instruction is a swapped predicate of the main cmp instruction, need to generate alternate instruction, not the one with the swapped predicate. Also, the lane with the alternate opcode should be selected only, if the corresponding operands are not compatible. Correctness confirmed: https://alive2.llvm.org/ce/z/94BG66 Differential Revision: https://reviews.llvm.org/D119855
48 lines
2.0 KiB
LLVM
48 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -mtriple=x86_64-unknown -slp-vectorizer -S | FileCheck %s
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define i16 @test(i16 %call37) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CALL:%.*]] = load i16, i16* undef, align 2
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i16> <i16 poison, i16 0, i16 0, i16 0, i16 poison, i16 0, i16 0, i16 0>, i16 [[CALL37:%.*]], i32 4
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[TMP0]], i16 [[CALL]], i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 0, i16 0, i16 poison, i16 0>, i16 [[CALL37]], i32 3
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> [[TMP2]], i16 [[CALL37]], i32 6
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; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <8 x i16> [[TMP1]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt <8 x i16> [[TMP1]], [[TMP3]]
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; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x i1> [[TMP4]], <8 x i1> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 11, i32 12, i32 5, i32 14, i32 7>
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; CHECK-NEXT: [[TMP7:%.*]] = zext <8 x i1> [[TMP6]] to <8 x i16>
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; CHECK-NEXT: [[TMP8:%.*]] = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> [[TMP7]])
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; CHECK-NEXT: [[OP_EXTRA:%.*]] = add i16 [[TMP8]], 0
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; CHECK-NEXT: ret i16 [[OP_EXTRA]]
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;
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entry:
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%call = load i16, i16* undef, align 2
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%0 = icmp slt i16 %call, 0
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%cond = zext i1 %0 to i16
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%1 = add i16 %cond, 0
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%2 = icmp slt i16 0, 0
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%cond32 = zext i1 %2 to i16
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%3 = add i16 %1, %cond32
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%.not = icmp sgt i16 0, %call37
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%cond55 = zext i1 %.not to i16
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%4 = icmp sgt i16 %call37, 0
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%cond76 = zext i1 %4 to i16
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%5 = icmp slt i16 0, 0
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%cond97 = zext i1 %5 to i16
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%.not206 = icmp sgt i16 0, %call37
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%cond120 = zext i1 %.not206 to i16
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%6 = icmp sgt i16 0, 0
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%cond141 = zext i1 %6 to i16
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%7 = icmp slt i16 0, 0
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%cond162 = zext i1 %7 to i16
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%8 = add i16 %3, %cond97
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%9 = add i16 %8, %cond55
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%10 = add i16 %9, %cond76
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%11 = add i16 %10, %cond162
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%12 = add i16 %11, %cond120
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%13 = add i16 %12, %cond141
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ret i16 %13
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}
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