82c8aca934
I strongly believe we need some variant of this. The main problem is e.g. that the glibc's assert has 4 parameters, but the profitability check is only okay with one extra phi node, so D116692 doesn't even trigger on most of the expected cases. While that restriction probably makes sense in normal code, if we are about to run off of a cliff (into an `unreachable`), this successor block is unlikely so the cost to setup these PHI nodes should not be on the hotpath, and shouldn't matter performance-wise. Likewise, we don't sink if there are unconditional predecessors UNLESS we'd sink at least one non-speculatable instruction, which is a performance workaround, but if we are about to run into `unreachable`, it shouldn't matter. Note that we only allow the case where there are at most unconditiona branches on the way to the unreachable block. Differential Revision: https://reviews.llvm.org/D117045
125 lines
4.0 KiB
LLVM
125 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -sink-common-insts -S | FileCheck %s
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; RUN: opt < %s -passes='simplifycfg<sink-common-insts>' -S | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-pc-linux-gnu"
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; `unreachable` block has conditional predecessors,
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; but everything we'd sink from unconditional predecessors are speculatable.
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; Also, too many phi's would normally be needed.
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define void @t0(i4 %cond, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {
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; CHECK-LABEL: @t0(
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; CHECK-NEXT: switch i4 [[COND:%.*]], label [[END:%.*]] [
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; CHECK-NEXT: i4 0, label [[END_SINK_SPLIT:%.*]]
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; CHECK-NEXT: i4 -1, label [[END_SINK_SPLIT]]
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; CHECK-NEXT: i4 1, label [[BB1:%.*]]
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; CHECK-NEXT: i4 -2, label [[BB1]]
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; CHECK-NEXT: ]
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; CHECK: bb1:
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; CHECK-NEXT: br label [[END_SINK_SPLIT]]
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; CHECK: end.sink.split:
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; CHECK-NEXT: [[H_SINK:%.*]] = phi i32 [ [[H:%.*]], [[BB1]] ], [ [[E:%.*]], [[TMP0:%.*]] ], [ [[E]], [[TMP0]] ]
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; CHECK-NEXT: [[G_SINK:%.*]] = phi i32 [ [[G:%.*]], [[BB1]] ], [ [[D:%.*]], [[TMP0]] ], [ [[D]], [[TMP0]] ]
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; CHECK-NEXT: [[V4:%.*]] = add i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[V5:%.*]] = add i32 [[V4]], [[C:%.*]]
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; CHECK-NEXT: [[V6:%.*]] = add i32 [[G_SINK]], [[H_SINK]]
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; CHECK-NEXT: [[R7:%.*]] = add i32 [[V5]], [[V6]]
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; CHECK-NEXT: call void @use32(i32 [[R7]])
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; CHECK-NEXT: unreachable
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; CHECK: end:
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; CHECK-NEXT: unreachable
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;
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switch i4 %cond, label %end [
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i4 0, label %bb0
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i4 -1, label %bb0
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i4 1, label %bb1
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i4 -2, label %bb1
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]
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bb0:
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%v0 = add i32 %a, %b
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%v1 = add i32 %v0, %c
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%v2 = add i32 %d, %e
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%r3 = add i32 %v1, %v2
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call void @use32(i32 %r3)
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br label %end
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bb1:
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%v4 = add i32 %a, %b
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%v5 = add i32 %v4, %c
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%v6 = add i32 %g, %h
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%r7 = add i32 %v5, %v6
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call void @use32(i32 %r7)
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br label %end
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end:
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unreachable
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}
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; Same, as @t0, but there's also a loop.
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define void @t1(i4 %cond, i1 %cond.loop, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {
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; CHECK-LABEL: @t1(
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; CHECK-NEXT: switch i4 [[COND:%.*]], label [[END_EARLY:%.*]] [
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; CHECK-NEXT: i4 0, label [[BB0:%.*]]
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; CHECK-NEXT: i4 -1, label [[BB0]]
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; CHECK-NEXT: i4 1, label [[BB1:%.*]]
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; CHECK-NEXT: i4 -2, label [[BB1]]
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; CHECK-NEXT: ]
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; CHECK: bb0:
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; CHECK-NEXT: [[V0:%.*]] = add i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[V1:%.*]] = add i32 [[V0]], [[C:%.*]]
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; CHECK-NEXT: [[V2:%.*]] = add i32 [[D:%.*]], [[E:%.*]]
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; CHECK-NEXT: [[R3:%.*]] = add i32 [[V1]], [[V2]]
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; CHECK-NEXT: call void @use32(i32 [[R3]])
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; CHECK-NEXT: br label [[END_EARLY]]
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; CHECK: bb1:
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; CHECK-NEXT: [[V4:%.*]] = add i32 [[A]], [[B]]
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; CHECK-NEXT: [[V5:%.*]] = add i32 [[V4]], [[C]]
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; CHECK-NEXT: [[V6:%.*]] = add i32 [[G:%.*]], [[H:%.*]]
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; CHECK-NEXT: [[R7:%.*]] = add i32 [[V5]], [[V6]]
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; CHECK-NEXT: call void @use32(i32 [[R7]])
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; CHECK-NEXT: br label [[END_EARLY]]
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; CHECK: end.early:
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; CHECK-NEXT: call void @sideeffect()
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; CHECK-NEXT: br i1 [[COND_LOOP:%.*]], label [[END_EARLY]], label [[END:%.*]]
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; CHECK: end:
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; CHECK-NEXT: call void @sideeffect()
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; CHECK-NEXT: unreachable
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;
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switch i4 %cond, label %end.early [
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i4 0, label %bb0
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i4 -1, label %bb0
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i4 1, label %bb1
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i4 -2, label %bb1
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]
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bb0:
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%v0 = add i32 %a, %b
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%v1 = add i32 %v0, %c
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%v2 = add i32 %d, %e
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%r3 = add i32 %v1, %v2
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call void @use32(i32 %r3)
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br label %end.early
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bb1:
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%v4 = add i32 %a, %b
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%v5 = add i32 %v4, %c
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%v6 = add i32 %g, %h
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%r7 = add i32 %v5, %v6
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call void @use32(i32 %r7)
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br label %end.early
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end.early:
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call void @sideeffect()
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br i1 %cond.loop, label %end.early, label %end
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end:
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call void @sideeffect()
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unreachable
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}
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declare void @use32(i32) speculatable
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declare void @sideeffect()
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