ff4b1d379f
This changes the approach taken to tail-merge the blocks to always create a new block instead of trying to reuse some block, and generalizes it to support dealing not with just the `ret` in the future. This effectively lifts the CallBr restriction, although this isn't really intentional. That is the only non-NFC change here, i'm not sure if it's reasonable/feasible to temporarily retain it. Other restrictions of the transform remain. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D104598
48 lines
1.6 KiB
LLVM
48 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
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; We're sign extending an 8-bit value.
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; The switch condition must be in the range [-128, 127], so any cases outside of that range must be dead.
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; Only the first case has a non-zero weight, but that gets eliminated. Note
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; that this shouldn't have been the case in the first place, but the test here
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; ensures that all-zero branch weights are not attached causing problems downstream.
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define i1 @repeated_signbits(i8 %condition) {
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; CHECK-LABEL: @repeated_signbits(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32
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; CHECK-NEXT: switch i32 [[SEXT]], label [[DEFAULT:%.*]] [
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; CHECK-NEXT: i32 0, label [[COMMON_RET:%.*]]
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; CHECK-NEXT: i32 127, label [[COMMON_RET]]
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; CHECK-NEXT: i32 -128, label [[COMMON_RET]]
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; CHECK-NEXT: i32 -1, label [[COMMON_RET]]
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; CHECK-NEXT: ]
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; CHECK: common.ret:
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; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ false, [[DEFAULT]] ], [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
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; CHECK-NEXT: ret i1 [[COMMON_RET_OP]]
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; CHECK: default:
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; CHECK-NEXT: br label [[COMMON_RET]]
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;
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entry:
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%sext = sext i8 %condition to i32
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switch i32 %sext, label %default [
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i32 -2147483648, label %a
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i32 -129, label %a
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i32 -128, label %a
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i32 -1, label %a
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i32 0, label %a
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i32 127, label %a
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i32 128, label %a
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i32 2147483647, label %a
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], !prof !1
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a:
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ret i1 1
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default:
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ret i1 0
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}
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!1 = !{!"branch_weights", i32 0, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0}
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