916f3e16bd
In the long run, we want to unify the dot product codegen solutions between all target architectures, but this intrinsic enables experimenting with AVX specific implementations in the meantime. Reviewed By: nicolasvasilache Differential Revision: https://reviews.llvm.org/D100593
65 lines
2.8 KiB
MLIR
65 lines
2.8 KiB
MLIR
// RUN: mlir-opt -verify-diagnostics %s | mlir-opt | FileCheck %s
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// CHECK-LABEL: func @avx512_mask_rndscale
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func @avx512_mask_rndscale(%a: vector<16xf32>, %b: vector<8xf64>, %i32: i32, %i16: i16, %i8: i8)
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-> (vector<16xf32>, vector<8xf64>)
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{
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// CHECK: x86vector.avx512.mask.rndscale {{.*}}: vector<16xf32>
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%0 = x86vector.avx512.mask.rndscale %a, %i32, %a, %i16, %i32 : vector<16xf32>
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// CHECK: x86vector.avx512.mask.rndscale {{.*}}: vector<8xf64>
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%1 = x86vector.avx512.mask.rndscale %b, %i32, %b, %i8, %i32 : vector<8xf64>
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return %0, %1: vector<16xf32>, vector<8xf64>
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}
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// CHECK-LABEL: func @avx512_scalef
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func @avx512_scalef(%a: vector<16xf32>, %b: vector<8xf64>, %i32: i32, %i16: i16, %i8: i8)
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-> (vector<16xf32>, vector<8xf64>)
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{
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// CHECK: x86vector.avx512.mask.scalef {{.*}}: vector<16xf32>
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%0 = x86vector.avx512.mask.scalef %a, %a, %a, %i16, %i32: vector<16xf32>
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// CHECK: x86vector.avx512.mask.scalef {{.*}}: vector<8xf64>
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%1 = x86vector.avx512.mask.scalef %b, %b, %b, %i8, %i32 : vector<8xf64>
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return %0, %1: vector<16xf32>, vector<8xf64>
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}
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// CHECK-LABEL: func @avx512_vp2intersect
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func @avx512_vp2intersect(%a: vector<16xi32>, %b: vector<8xi64>)
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-> (vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>)
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{
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// CHECK: x86vector.avx512.vp2intersect {{.*}} : vector<16xi32>
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%0, %1 = x86vector.avx512.vp2intersect %a, %a : vector<16xi32>
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// CHECK: x86vector.avx512.vp2intersect {{.*}} : vector<8xi64>
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%2, %3 = x86vector.avx512.vp2intersect %b, %b : vector<8xi64>
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return %0, %1, %2, %3 : vector<16xi1>, vector<16xi1>, vector<8xi1>, vector<8xi1>
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}
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// CHECK-LABEL: func @avx512_mask_compress
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func @avx512_mask_compress(%k1: vector<16xi1>, %a1: vector<16xf32>,
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%k2: vector<8xi1>, %a2: vector<8xi64>)
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-> (vector<16xf32>, vector<16xf32>, vector<8xi64>)
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{
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// CHECK: x86vector.avx512.mask.compress {{.*}} : vector<16xf32>
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%0 = x86vector.avx512.mask.compress %k1, %a1 : vector<16xf32>
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// CHECK: x86vector.avx512.mask.compress {{.*}} : vector<16xf32>
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%1 = x86vector.avx512.mask.compress %k1, %a1 {constant_src = dense<5.0> : vector<16xf32>} : vector<16xf32>
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// CHECK: x86vector.avx512.mask.compress {{.*}} : vector<8xi64>
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%2 = x86vector.avx512.mask.compress %k2, %a2, %a2 : vector<8xi64>, vector<8xi64>
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return %0, %1, %2 : vector<16xf32>, vector<16xf32>, vector<8xi64>
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}
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// CHECK-LABEL: func @avx_rsqrt
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func @avx_rsqrt(%a: vector<8xf32>) -> (vector<8xf32>)
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{
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// CHECK: x86vector.avx.rsqrt {{.*}} : vector<8xf32>
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%0 = x86vector.avx.rsqrt %a : vector<8xf32>
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return %0 : vector<8xf32>
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}
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// CHECK-LABEL: func @avx_dot
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func @avx_dot(%a: vector<8xf32>, %b: vector<8xf32>) -> (vector<8xf32>)
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{
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// CHECK: x86vector.avx.intr.dot {{.*}} : vector<8xf32>
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%0 = x86vector.avx.intr.dot %a, %b : vector<8xf32>
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return %0 : vector<8xf32>
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}
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