b2729fda60
This revision follows up on the conversation titled: ```[llvm-dev] Understanding and controlling some of the AVX shuffle emission paths``` The revision adds a vblendps-based implementation for transpose8x8 and further distinguishes between and intrinsics and an inline_asm implementation. This results in roughly 20% fewer cycles as reported by llvm-mca: After this revision (intrinsic version, resolves to virtually identical assembly as per the llvm-dev discussion, no vblendps instruction is emitted): ``` Iterations: 100 Instructions: 5900 Total Cycles: 2415 Total uOps: 7300 Dispatch Width: 6 uOps Per Cycle: 3.02 IPC: 2.44 Block RThroughput: 24.0 Cycles with backend pressure increase [ 89.90% ] Throughput Bottlenecks: Resource Pressure [ 89.65% ] - SKXPort1 [ 0.04% ] - SKXPort2 [ 12.42% ] - SKXPort3 [ 12.42% ] - SKXPort5 [ 89.52% ] Data Dependencies: [ 37.06% ] - Register Dependencies [ 37.06% ] - Memory Dependencies [ 0.00% ] ``` After this revision (inline_asm version, vblendps instructions are indeed emitted): ``` Iterations: 100 Instructions: 6300 Total Cycles: 2015 Total uOps: 7700 Dispatch Width: 6 uOps Per Cycle: 3.82 IPC: 3.13 Block RThroughput: 20.0 Cycles with backend pressure increase [ 83.47% ] Throughput Bottlenecks: Resource Pressure [ 83.18% ] - SKXPort0 [ 14.49% ] - SKXPort1 [ 14.54% ] - SKXPort2 [ 19.70% ] - SKXPort3 [ 19.70% ] - SKXPort5 [ 83.03% ] - SKXPort6 [ 14.49% ] Data Dependencies: [ 39.75% ] - Register Dependencies [ 39.75% ] - Memory Dependencies [ 0.00% ] ``` An accessible copy of the conversation is available [here](https://gist.github.com/nicolasvasilache/68c7f34012584b0e00f335bcb374ede0). Differential Revision: https://reviews.llvm.org/D114393
57 lines
2.2 KiB
MLIR
57 lines
2.2 KiB
MLIR
// RUN: mlir-opt %s -convert-vector-to-llvm | \
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// RUN: mlir-cpu-runner -e entry_point_with_all_constants -entry-point-result=void \
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// RUN: -shared-libs=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext
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module {
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llvm.func @function_to_run(%a: vector<8xf32>, %b: vector<8xf32>) {
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// CHECK: ( 8, 10, 12, 14, 16, 18, 20, 22 )
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%r0 = llvm.inline_asm asm_dialect = intel
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"vaddps $0, $1, $2", "=x,x,x" %a, %b:
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(vector<8xf32>, vector<8xf32>) -> vector<8xf32>
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vector.print %r0: vector<8xf32>
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// vblendps implemented with inline_asm.
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// CHECK: ( 0, 1, 10, 11, 4, 5, 14, 15 )
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%r1 = llvm.inline_asm asm_dialect = intel
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"vblendps $0, $1, $2, 0xCC", "=x,x,x" %a, %b:
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(vector<8xf32>, vector<8xf32>) -> vector<8xf32>
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vector.print %r1: vector<8xf32>
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// vblendps 0xCC via vector.shuffle (emulates clang intrinsics impl)
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// CHECK: ( 0, 1, 10, 11, 4, 5, 14, 15 )
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%r2 = vector.shuffle %a, %b[0, 1, 10, 11, 4, 5, 14, 15]
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: vector<8xf32>, vector<8xf32>
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vector.print %r2: vector<8xf32>
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// vblendps 0x33 implemented with inline_asm.
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// CHECK: ( 8, 9, 2, 3, 12, 13, 6, 7 )
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%r3 = llvm.inline_asm asm_dialect = intel
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"vblendps $0, $1, $2, 0x33", "=x,x,x" %a, %b:
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(vector<8xf32>, vector<8xf32>) -> vector<8xf32>
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vector.print %r3: vector<8xf32>
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// vblendps 0x33 via vector.shuffle (emulates clang intrinsics impl)
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// CHECK: ( 8, 9, 2, 3, 12, 13, 6, 7 )
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%r4 = vector.shuffle %a, %b[8, 9, 2, 3, 12, 13, 6, 7]
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: vector<8xf32>, vector<8xf32>
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vector.print %r4: vector<8xf32>
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llvm.return
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}
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// Solely exists to prevent inlining and get the expected assembly.
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llvm.func @entry_point(%a: vector<8xf32>, %b: vector<8xf32>) {
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llvm.call @function_to_run(%a, %b) : (vector<8xf32>, vector<8xf32>) -> ()
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llvm.return
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}
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llvm.func @entry_point_with_all_constants() {
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%a = llvm.mlir.constant(dense<[0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0]>
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: vector<8xf32>) : vector<8xf32>
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%b = llvm.mlir.constant(dense<[8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0]>
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: vector<8xf32>) : vector<8xf32>
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llvm.call @function_to_run(%a, %b) : (vector<8xf32>, vector<8xf32>) -> ()
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llvm.return
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}
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}
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