303c180199
LLVM so far has only supported the MIPS-II and above architectures. MIPS-II is pretty close to MIPS-I, the major difference being that "load" instructions always take one extra instruction slot to propogate to registers. This patch adds support for MIPS-I by adding hazard handling for load delay slots, alongside MIPSR6 forbidden slots and FPU slots, inserting a NOP instruction between a load and any instruction immediately following that reads the load's destination register. I also included a simple regression test. Since no existing tests target MIPS-I, those all still pass. Issue ref: https://github.com/simias/psx-sdk-rs/issues/1 I also tested by building a simple demo app with Clang and running it in an emulator. Patch by: @impiaaa Differential Revision: https://reviews.llvm.org/D122427
71 lines
2.9 KiB
LLVM
71 lines
2.9 KiB
LLVM
; Check that the CPU names work.
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; RUN: llc -mtriple=mips -mcpu=generic -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=GENERIC
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; GENERIC: ISA: MIPS32
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; RUN: llc -mtriple=mips -mcpu=mips1 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS1
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; MIPS1: ISA: MIPS1
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; RUN: llc -mtriple=mips -mcpu=mips2 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS2
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; MIPS2: ISA: MIPS2
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; RUN: llc -mtriple=mips64 -mcpu=mips3 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS3
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; MIPS3: ISA: MIPS3
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; RUN: llc -mtriple=mips64 -mcpu=mips4 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS4
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; MIPS4: ISA: MIPS4
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; RUN: llc -mtriple=mips -mcpu=mips32 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32
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; MIPS32: ISA: MIPS32
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; RUN: llc -mtriple=mips -mcpu=mips32r2 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32R2
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; MIPS32R2: ISA: MIPS32r2
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; RUN: llc -mtriple=mips -mcpu=mips32r3 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32R3
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; MIPS32R3: ISA: MIPS32r3
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; RUN: llc -mtriple=mips -mcpu=mips32r5 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32R5
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; MIPS32R5: ISA: MIPS32r5
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; RUN: llc -mtriple=mips -mcpu=mips32r6 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS32R6
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; MIPS32R6: ISA: MIPS32r6
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; RUN: llc -mtriple=mips64 -mcpu=mips64 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64
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; MIPS64: ISA: MIPS64
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; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64R2
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; MIPS64R2: ISA: MIPS64r2
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; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64R3
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; MIPS64R3: ISA: MIPS64r3
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; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64R5
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; MIPS64R5: ISA: MIPS64r5
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; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=MIPS64R6
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; MIPS64R6: ISA: MIPS64r6
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; RUN: llc -mtriple=mips64 -mcpu=octeon -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=OCTEON
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; OCTEON: ISA: MIPS64r2
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; OCTEON: ISA Extension: Cavium Networks Octeon
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; RUN: llc -mtriple=mips64 -mcpu=octeon+ -filetype=obj < %s \
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; RUN: | llvm-readelf -A - | FileCheck %s --check-prefix=OCTEONP
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; OCTEONP: ISA: MIPS64r2
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; OCTEONP: ISA Extension: Cavium Networks OcteonP
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; Check that we reject CPUs that are not implemented.
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; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 \
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; RUN: | FileCheck %s --check-prefix=ERROR
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; ERROR: LLVM ERROR: Code generation for MIPS-{{.}} is not implemented
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define void @foo() {
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ret void
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}
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