a919d3d888
Issue: https://github.com/llvm/llvm-project/issues/54431 PHINodes that need to be generated to accommodate a PHINode outside the region due to different output paths need to have their own numbering to determine the number of output schemes required to properly handle all the outlined regions. This numbering was previously only determined by the order and values of the incoming values, as well as the parent block of the PHINode. This adds the incoming blocks to the calculation of a hash value for these PHINodes as well, and the supporting infrastructure to give each block in a region a corresponding canonical numbering. Reviewer: paquette Differential Revision: https://reviews.llvm.org/D122207
123 lines
4.2 KiB
LLVM
123 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs
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; RUN: opt -S -verify -iroutliner -ir-outlining-no-cost < %s | FileCheck %s
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; A PHINode defines the global value number of a split phi node for
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; an exit paths based on the canonical number for the incoming values, and
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; the canonical number for the basic block. This checks that we accurately
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; capture a different numbering for the same incoming value but with different
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; blocks.
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define void @func1(i32 %0, i32 %1) local_unnamed_addr #0 {
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bb1:
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br label %bb5
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bb2:
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%a = add i32 %0, %1
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%b = add i32 %0, %1
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%c = icmp eq i32 %b, 1
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br i1 %c, label %bb5, label %bb3
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bb3:
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%d = add i32 %0, %1
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br label %bb5
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bb4:
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%e = sub i32 %0, %1
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br label %bb2
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bb5:
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%f = phi i32 [ 0, %bb1 ], [ 1, %bb2 ], [ 1, %bb3 ]
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ret void
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}
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define void @func2(i32 %0, i32 %1) local_unnamed_addr #0 {
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bb1:
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br label %bb5
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bb2:
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%a = sub i32 %0, %1
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%b = add i32 %0, %1
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%c = icmp eq i32 %b, 1
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br i1 %c, label %bb5, label %bb3
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bb3:
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%d = add i32 %0, %1
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br label %bb5
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bb4:
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%e = add i32 %0, %1
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br label %bb2
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bb5:
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%f = phi i32 [ 0, %bb1 ], [ 1, %bb3 ], [ 1, %bb2 ]
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ret void
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}
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; CHECK-LABEL: @func1(
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; CHECK-NEXT: bb1:
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; CHECK-NEXT: [[F_CE_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BB5:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: [[A:%.*]] = add i32 [[TMP0:%.*]], [[TMP1:%.*]]
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; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[F_CE_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], i32* [[F_CE_LOC]], i32 0)
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; CHECK-NEXT: [[F_CE_RELOAD:%.*]] = load i32, i32* [[F_CE_LOC]], align 4
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: br label [[BB5]]
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; CHECK: bb4:
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; CHECK-NEXT: [[E:%.*]] = sub i32 [[TMP0]], [[TMP1]]
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; CHECK-NEXT: br label [[BB2:%.*]]
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; CHECK: bb5:
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; CHECK-NEXT: [[F:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[F_CE_RELOAD]], [[BB2]] ]
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: @func2(
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; CHECK-NEXT: bb1:
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; CHECK-NEXT: [[F_CE_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BB5:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: [[A:%.*]] = sub i32 [[TMP0:%.*]], [[TMP1:%.*]]
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; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[F_CE_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: call void @outlined_ir_func_0(i32 [[TMP0]], i32 [[TMP1]], i32* [[F_CE_LOC]], i32 1)
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; CHECK-NEXT: [[F_CE_RELOAD:%.*]] = load i32, i32* [[F_CE_LOC]], align 4
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: br label [[BB5]]
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; CHECK: bb4:
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; CHECK-NEXT: [[E:%.*]] = add i32 [[TMP0]], [[TMP1]]
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; CHECK-NEXT: br label [[BB2:%.*]]
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; CHECK: bb5:
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; CHECK-NEXT: [[F:%.*]] = phi i32 [ 0, [[BB1:%.*]] ], [ [[F_CE_RELOAD]], [[BB2]] ]
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: define internal void @outlined_ir_func_0(
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; CHECK-NEXT: newFuncRoot:
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; CHECK-NEXT: br label [[BB2_TO_OUTLINE:%.*]]
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; CHECK: bb2_to_outline:
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; CHECK-NEXT: [[B:%.*]] = add i32 [[TMP0:%.*]], [[TMP1:%.*]]
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B]], 1
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; CHECK-NEXT: br i1 [[C]], label [[BB5_SPLIT:%.*]], label [[BB3:%.*]]
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; CHECK: bb3:
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; CHECK-NEXT: [[D:%.*]] = add i32 [[TMP0]], [[TMP1]]
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; CHECK-NEXT: br label [[BB5_SPLIT]]
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; CHECK: bb5.split:
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; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ 1, [[BB3]] ], [ 1, [[BB2_TO_OUTLINE]] ]
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; CHECK-NEXT: [[F_CE:%.*]] = phi i32 [ 1, [[BB2_TO_OUTLINE]] ], [ 1, [[BB3]] ]
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; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]]
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; CHECK: bb5.exitStub:
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; CHECK-NEXT: switch i32 [[TMP3:%.*]], label [[FINAL_BLOCK_0:%.*]] [
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; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]]
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; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_0:%.*]]
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; CHECK-NEXT: ]
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; CHECK: output_block_0_0:
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; CHECK-NEXT: store i32 [[F_CE]], i32* [[TMP2:%.*]], align 4
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; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
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; CHECK: output_block_1_0:
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; CHECK-NEXT: store i32 [[TMP4]], i32* [[TMP2]], align 4
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; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
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; CHECK: final_block_0:
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; CHECK-NEXT: ret void
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;
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