Matt Arsenault bf1bf706c8 AMDGPU/GlobalISel: Add regbankselect test for phis ...

Add baseline for future fixes. These mostly show how this is broken
and producing illegal situations.

llvm-svn: 355057

2019-02-28 00:52:36 +00:00

..

AArch64

[AArch64] Generate FP16 vector compare instructions.

2019-02-28 00:31:38 +00:00

AMDGPU

AMDGPU/GlobalISel: Add regbankselect test for phis

2019-02-28 00:52:36 +00:00

ARC

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ARM

[ARM] Add Cortex-M35P

2019-02-26 12:02:12 +00:00

AVR

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BPF

[BPF] Don't fail for static variables

2019-02-27 05:36:15 +00:00

Generic

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Hexagon

[Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trap

2019-02-21 19:42:39 +00:00

Inputs

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Lanai

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Mips

[MIPS GlobalISel] Select G_UADDO

2019-02-26 17:22:42 +00:00

MIR

[X86] Add FPCW as an implicit use on floating point load instructions.

2019-02-08 20:50:09 +00:00

MSP430

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NVPTX

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PowerPC

Default to Secure PLT on PPC for NetBSD and OpenBSD.

2019-02-27 21:53:14 +00:00

RISCV

[RISCV] Re-organise calling convention tests

2019-02-19 13:47:19 +00:00

SPARC

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SystemZ

[SystemZ] Pass regalloc hints to help Load-and-Test transformations.

2019-02-27 00:18:28 +00:00

Thumb

[ARM] Add some more missing T1 opcodes for the peephole optimisier

2019-02-25 15:50:54 +00:00

Thumb2

[ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs

2019-02-22 12:23:31 +00:00

WebAssembly

[WebAssembly] Fix ScopeTops info in CFGStackify for EH pads

2019-02-27 01:35:14 +00:00

WinCFGuard

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WinEH

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X86

[X86][AVX] Only combine loads to broadcasts for legal types

2019-02-27 11:17:25 +00:00

XCore

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