9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
55 lines
1.3 KiB
LLVM
55 lines
1.3 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=5 < %s | FileCheck -check-prefix=GCN %s
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; Restrict maximum branch to between +15 and -16 dwords
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; Instructions inside a bundle were collectively counted as
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; 0-bytes. Make sure this is accounted for when estimating branch
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; distances
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; Bundle used for address in call sequence: 20 bytes
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; s_getpc_b64
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; s_add_u32
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; s_addc_u32
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; plus additional overhead
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; s_setpc_b64
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; and some register copies
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declare void @func() #0
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; GCN-LABEL: {{^}}bundle_size:
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; GCN: s_cbranch_scc0 [[BB_EXPANSION:.LBB[0-9]+_[0-9]+]]
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; GCN: s_getpc_b64
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; GCN-NEXT: .Lpost_getpc{{[0-9]+}}:{{$}}
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; GCN-NEXT: s_add_u32
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; GCN-NEXT: s_addc_u32
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; GCN-NEXT: s_setpc_b64
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; GCN: {{^}}[[BB_EXPANSION]]:
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; GCN: s_getpc_b64
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; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, func@
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; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, func@
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; GCN: s_swappc_b64
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define amdgpu_kernel void @bundle_size(ptr addrspace(1) %arg, i32 %cnd) #0 {
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bb:
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%cmp = icmp eq i32 %cnd, 0
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br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
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bb2:
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call void @func()
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call void asm sideeffect
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"v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", ""() #0
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br label %bb3
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bb3:
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store volatile i32 %cnd, ptr addrspace(1) %arg
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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