9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
137 lines
6.2 KiB
LLVM
137 lines
6.2 KiB
LLVM
; RUN: llc -global-isel=0 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
|
|
; RUN: llc -global-isel=1 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
|
|
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
|
|
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
|
|
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s
|
|
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s
|
|
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s
|
|
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add:
|
|
; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN-DAG: s_mov_b32 m0,
|
|
; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
|
|
define amdgpu_kernel void @ds_ordered_add(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
|
|
%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
|
|
store i32 %val, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; Below are various modifications of input operands and shader types.
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_counter2:
|
|
; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN-DAG: s_mov_b32 m0,
|
|
; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:776 gds
|
|
define amdgpu_kernel void @ds_ordered_add_counter2(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
|
|
%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 2, i1 true, i1 true)
|
|
store i32 %val, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_nodone:
|
|
; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN-DAG: s_mov_b32 m0,
|
|
; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:260 gds
|
|
define amdgpu_kernel void @ds_ordered_add_nodone(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
|
|
%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 false)
|
|
store i32 %val, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_norelease:
|
|
; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN-DAG: s_mov_b32 m0,
|
|
; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:4 gds
|
|
define amdgpu_kernel void @ds_ordered_add_norelease(ptr addrspace(2) inreg %gds, ptr addrspace(1) %out) {
|
|
%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 false, i1 false)
|
|
store i32 %val, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_cs:
|
|
; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN: s_mov_b32 m0, s0
|
|
; VIGFX9-NEXT: s_nop 0
|
|
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
|
|
; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
|
|
define amdgpu_cs float @ds_ordered_add_cs(ptr addrspace(2) inreg %gds) {
|
|
%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
|
|
%r = bitcast i32 %val to float
|
|
ret float %r
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_default_cc:
|
|
; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN: s_mov_b32 m0, 0{{$}}
|
|
; VIGFX9-NEXT: s_nop 0
|
|
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
|
|
; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
|
|
define float @ds_ordered_add_default_cc() {
|
|
%val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
|
|
%r = bitcast i32 %val to float
|
|
ret float %r
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_fastcc:
|
|
; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN: s_mov_b32 m0, 0{{$}}
|
|
; VIGFX9-NEXT: s_nop 0
|
|
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
|
|
; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
|
|
define fastcc float @ds_ordered_add_fastcc() {
|
|
%val = call i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
|
|
%r = bitcast i32 %val to float
|
|
ret float %r
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_func:
|
|
; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN: s_mov_b32 m0, 0{{$}}
|
|
; VIGFX9-NEXT: s_nop 0
|
|
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
|
|
; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
|
|
define float @ds_ordered_add_func() {
|
|
%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) null, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
|
|
%r = bitcast i32 %val to float
|
|
ret float %r
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_ps:
|
|
; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN: s_mov_b32 m0, s0
|
|
; VIGFX9-NEXT: s_nop 0
|
|
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:1796 gds
|
|
; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
|
|
define amdgpu_ps float @ds_ordered_add_ps(ptr addrspace(2) inreg %gds) {
|
|
%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
|
|
%r = bitcast i32 %val to float
|
|
ret float %r
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_vs:
|
|
; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN: s_mov_b32 m0, s0
|
|
; VIGFX9-NEXT: s_nop 0
|
|
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:2820 gds
|
|
; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
|
|
define amdgpu_vs float @ds_ordered_add_vs(ptr addrspace(2) inreg %gds) {
|
|
%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
|
|
%r = bitcast i32 %val to float
|
|
ret float %r
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}ds_ordered_add_gs:
|
|
; GCN: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
|
|
; GCN: s_mov_b32 m0, s0
|
|
; VIGFX9-NEXT: s_nop 0
|
|
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:3844 gds
|
|
; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
|
|
define amdgpu_gs float @ds_ordered_add_gs(ptr addrspace(2) inreg %gds) {
|
|
%val = call i32@llvm.amdgcn.ds.ordered.add(ptr addrspace(2) %gds, i32 31, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
|
|
%r = bitcast i32 %val to float
|
|
ret float %r
|
|
}
|
|
|
|
declare i32 @llvm.amdgcn.ds.ordered.add(ptr addrspace(2) nocapture, i32, i32, i32, i1, i32, i1, i1)
|