9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
53 lines
2.1 KiB
LLVM
53 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}test1:
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; CHECK-NOT: s_waitcnt
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; CHECK: image_store
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0){{$}}
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; CHECK-NEXT: image_store
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <4 x float> %d0, <4 x float> %d1, i32 %c0, i32 %c1) {
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call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %d0, i32 15, i32 %c0, <8 x i32> %rsrc, i32 0, i32 0)
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call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00
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call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %d1, i32 15, i32 %c1, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; Test that the intrinsic is merged with automatically generated waits and
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; emitted as late as possible.
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;
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; CHECK-LABEL: {{^}}test2:
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; CHECK-NOT: s_waitcnt
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; CHECK: image_load
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; CHECK-NEXT: v_lshlrev_b32
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0){{$}}
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; CHECK-NEXT: image_store
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define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, i32 %c) {
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%t = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %c, <8 x i32> %rsrc, i32 0, i32 0)
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call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00
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%c.1 = mul i32 %c, 2
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call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %t, i32 15, i32 %c.1, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; CHECK-LABEL: {{^}}test3:
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; CHECK: image_load
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; CHECK: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK: image_store
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define amdgpu_ps void @test3(<8 x i32> inreg %rsrc, i32 %c) {
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%t = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %c, <8 x i32> %rsrc, i32 0, i32 0)
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call void @llvm.amdgcn.s.waitcnt(i32 49279) ; not isInt<16>, but isUInt<16>
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%c.1 = mul i32 %c, 2
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call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %t, i32 15, i32 %c.1, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.s.waitcnt(i32) #0
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declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #1
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declare void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float>, i32, i32, <8 x i32>, i32, i32) #0
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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