9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
49 lines
2.0 KiB
LLVM
49 lines
2.0 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs -amdgpu-scalar-ir-passes=false < %s | FileCheck -check-prefix=GCN %s
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; These tests are split out from umed3.ll and smed3.ll and use the
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; -amdgpu-scalar-ir-passes=false flag, because InstSimplify would constant
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; fold these functions otherwise.
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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; GCN-LABEL: {{^}}v_test_umed3_r_i_i_constant_order_i32:
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; GCN: v_max_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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; GCN: v_min_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_umed3_r_i_i_constant_order_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr i32, ptr addrspace(1) %aptr, i32 %tid
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%outgep = getelementptr i32, ptr addrspace(1) %out, i32 %tid
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%a = load i32, ptr addrspace(1) %gep0
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%icmp0 = icmp ugt i32 %a, 17
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%i0 = select i1 %icmp0, i32 %a, i32 17
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%icmp1 = icmp ult i32 %i0, 12
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%i1 = select i1 %icmp1, i32 %i0, i32 12
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store i32 %i1, ptr addrspace(1) %outgep
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ret void
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}
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; GCN-LABEL: {{^}}v_test_smed3_r_i_i_constant_order_i32:
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; GCN: v_max_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}}
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; GCN: v_min_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}}
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define amdgpu_kernel void @v_test_smed3_r_i_i_constant_order_i32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr i32, ptr addrspace(1) %aptr, i32 %tid
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%outgep = getelementptr i32, ptr addrspace(1) %out, i32 %tid
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%a = load i32, ptr addrspace(1) %gep0
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%icmp0 = icmp sgt i32 %a, 17
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%i0 = select i1 %icmp0, i32 %a, i32 17
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%icmp1 = icmp slt i32 %i0, 12
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%i1 = select i1 %icmp1, i32 %i0, i32 12
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store i32 %i1, ptr addrspace(1) %outgep
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ret void
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}
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