9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
293 lines
7.8 KiB
LLVM
293 lines
7.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}setcc_sgt_true_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_sgt_true_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp sgt i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_sgt_true_sext_swap:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_sgt_true_sext_swap(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp slt i32 -1, %ext
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ne_true_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ne_true_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ne i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ult_true_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ult_true_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ult i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_eq_true_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_eq_true_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp eq i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_sle_true_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_sle_true_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp sle i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_uge_true_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_uge_true_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp uge i32 %ext, -1
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_eq_false_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_eq_false_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp eq i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_sge_false_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_sge_false_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp sge i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ule_false_sext:
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; GCN: v_cmp_le_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ule_false_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ule i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ne_false_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ne_false_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ne i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_ugt_false_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_ugt_false_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp ugt i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}setcc_slt_false_sext:
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; GCN: v_cmp_gt_u32_e{{32|64}} [[CC:[^,]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-NEXT: s_and_saveexec_b64 {{[^,]+}}, [[CC]]
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; GCN-NOT: v_cndmask_
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define amdgpu_kernel void @setcc_slt_false_sext(ptr addrspace(1) nocapture %arg) {
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bb:
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%y = tail call i32 @llvm.amdgcn.workitem.id.y()
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%cmp = icmp ugt i32 %x, %y
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%ext = sext i1 %cmp to i32
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%cond = icmp slt i32 %ext, 0
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br i1 %cond, label %then, label %endif
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then:
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store i32 1, ptr addrspace(1) %arg, align 4
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br label %endif
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endif:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @llvm.amdgcn.workitem.id.y() #0
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attributes #0 = { nounwind readnone speculatable }
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