9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
288 lines
7.6 KiB
LLVM
288 lines
7.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s| FileCheck -check-prefixes=GCN,SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
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; XXX: Merge this into setcc, once R600 supports 64-bit operations
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;;;==========================================================================;;;
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;; Double comparisons
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;;;==========================================================================;;;
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; GCN-LABEL: {{^}}f64_oeq:
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; GCN: v_cmp_eq_f64
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define amdgpu_kernel void @f64_oeq(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp oeq double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_ogt:
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; GCN: v_cmp_gt_f64
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define amdgpu_kernel void @f64_ogt(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp ogt double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_oge:
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; GCN: v_cmp_ge_f64
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define amdgpu_kernel void @f64_oge(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp oge double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_olt:
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; GCN: v_cmp_lt_f64
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define amdgpu_kernel void @f64_olt(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp olt double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_ole:
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; GCN: v_cmp_le_f64
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define amdgpu_kernel void @f64_ole(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp ole double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_one:
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; GCN: v_cmp_lg_f64_e32 vcc
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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define amdgpu_kernel void @f64_one(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp one double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_ord:
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; GCN: v_cmp_o_f64
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define amdgpu_kernel void @f64_ord(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp ord double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_ueq:
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; GCN: v_cmp_nlg_f64_e32 vcc
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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define amdgpu_kernel void @f64_ueq(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp ueq double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_ugt:
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; GCN: v_cmp_nle_f64_e32 vcc
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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define amdgpu_kernel void @f64_ugt(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp ugt double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_uge:
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; GCN: v_cmp_nlt_f64_e32 vcc
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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define amdgpu_kernel void @f64_uge(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp uge double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_ult:
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; GCN: v_cmp_nge_f64_e32 vcc
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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define amdgpu_kernel void @f64_ult(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp ult double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_ule:
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; GCN: v_cmp_ngt_f64_e32 vcc
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
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define amdgpu_kernel void @f64_ule(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp ule double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_une:
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; GCN: v_cmp_neq_f64
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define amdgpu_kernel void @f64_une(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp une double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}f64_uno:
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; GCN: v_cmp_u_f64
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define amdgpu_kernel void @f64_uno(ptr addrspace(1) %out, double %a, double %b) #0 {
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entry:
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%tmp0 = fcmp uno double %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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;;;==========================================================================;;;
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;; 64-bit integer comparisons
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;;;==========================================================================;;;
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; GCN-LABEL: {{^}}i64_eq:
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; SI: v_cmp_eq_u64
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; VI: s_cmp_eq_u64
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define amdgpu_kernel void @i64_eq(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp eq i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i64_ne:
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; SI: v_cmp_ne_u64
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; VI: s_cmp_lg_u64
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define amdgpu_kernel void @i64_ne(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp ne i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i64_ugt:
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; GCN: v_cmp_gt_u64
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define amdgpu_kernel void @i64_ugt(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp ugt i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i64_uge:
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; GCN: v_cmp_ge_u64
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define amdgpu_kernel void @i64_uge(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp uge i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i64_ult:
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; GCN: v_cmp_lt_u64
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define amdgpu_kernel void @i64_ult(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp ult i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i64_ule:
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; GCN: v_cmp_le_u64
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define amdgpu_kernel void @i64_ule(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp ule i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i64_sgt:
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; GCN: v_cmp_gt_i64
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define amdgpu_kernel void @i64_sgt(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp sgt i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i64_sge:
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; GCN: v_cmp_ge_i64
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define amdgpu_kernel void @i64_sge(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp sge i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i64_slt:
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; GCN: v_cmp_lt_i64
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define amdgpu_kernel void @i64_slt(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp slt i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i64_sle:
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; GCN: v_cmp_le_i64
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define amdgpu_kernel void @i64_sle(ptr addrspace(1) %out, i64 %a, i64 %b) #0 {
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entry:
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%tmp0 = icmp sle i64 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i128_sle:
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; GCN: v_cmp_le_i64
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; CGV: v_cndmask
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; SI: v_cmp_eq_u64
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; VI: s_cmp_eq_u64
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define amdgpu_kernel void @i128_sle(ptr addrspace(1) %out, i128 %a, i128 %b) #0 {
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entry:
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%tmp0 = icmp sle i128 %a, %b
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}i128_eq_const:
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; SI: v_cmp_eq_u64
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; VI: s_cmp_eq_u64
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define amdgpu_kernel void @i128_eq_const(ptr addrspace(1) %out, i128 %a) #0 {
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entry:
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%tmp0 = icmp eq i128 %a, 85070591730234615865843651857942052992
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%tmp1 = sext i1 %tmp0 to i32
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { nounwind }
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