9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
44 lines
2.1 KiB
LLVM
44 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck %s
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; This test is for a bug in the machine scheduler where stores without
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; an underlying object would be moved across the barrier. In this
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; test, the <2 x i8> store will be split into two i8 stores, so they
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; won't have an underlying object.
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; CHECK-LABEL: {{^}}test:
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; CHECK: ds_write_b8
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; CHECK: ds_write_b8
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; CHECK: s_barrier
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; CHECK: s_endpgm
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; Function Attrs: nounwind
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define amdgpu_kernel void @test(ptr addrspace(3) nocapture %arg, ptr addrspace(1) nocapture readonly %arg1, ptr addrspace(1) nocapture readonly %arg2, ptr addrspace(1) nocapture %arg3, i32 %arg4, i64 %tmp9) #0 {
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bb:
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%tmp10 = getelementptr inbounds i32, ptr addrspace(1) %arg2, i64 %tmp9
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%tmp13 = load i32, ptr addrspace(1) %tmp10, align 2
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%tmp14 = getelementptr inbounds <2 x i8>, ptr addrspace(3) %arg, i32 %tmp13
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%tmp15 = load <2 x i8>, ptr addrspace(3) %tmp14, align 1
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%tmp16 = add i32 %tmp13, 1
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%tmp17 = getelementptr inbounds <2 x i8>, ptr addrspace(3) %arg, i32 %tmp16
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store <2 x i8> %tmp15, ptr addrspace(3) %tmp17, align 1
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tail call void @llvm.amdgcn.s.barrier()
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%tmp25 = load i32, ptr addrspace(1) %tmp10, align 4
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%tmp26 = sext i32 %tmp25 to i64
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%tmp27 = sext i32 %arg4 to i64
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%tmp28 = getelementptr inbounds <2 x i8>, ptr addrspace(3) %arg, i32 %tmp25, i32 %arg4
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%tmp29 = load i8, ptr addrspace(3) %tmp28, align 1
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%tmp30 = getelementptr inbounds <2 x i8>, ptr addrspace(1) %arg3, i64 %tmp26, i64 %tmp27
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store i8 %tmp29, ptr addrspace(1) %tmp30, align 1
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%tmp32 = getelementptr inbounds <2 x i8>, ptr addrspace(3) %arg, i32 %tmp25, i32 0
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%tmp33 = load i8, ptr addrspace(3) %tmp32, align 1
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%tmp35 = getelementptr inbounds <2 x i8>, ptr addrspace(1) %arg3, i64 %tmp26, i64 0
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store i8 %tmp33, ptr addrspace(1) %tmp35, align 1
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ret void
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}
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; Function Attrs: convergent nounwind
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declare void @llvm.amdgcn.s.barrier() #1
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attributes #0 = { nounwind }
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attributes #1 = { convergent nounwind }
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