da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
40 lines
1.6 KiB
LLVM
Executable File
40 lines
1.6 KiB
LLVM
Executable File
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @copy_to_scc(i32 addrspace(1)* %out, i32 addrspace(1)* %in, <4 x i32> addrspace(4)* %addrSrc) {
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; GCN-LABEL: copy_to_scc:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_load_dword v0, off, s[4:7], 0 offset:252
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; GCN-NEXT: s_load_dword s2, s[2:3], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_lg_u32 s2, 0
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; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], vcc
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; GCN-NEXT: s_and_b64 s[2:3], s[2:3], exec
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; GCN-NEXT: s_cselect_b32 s2, 2, 3
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; GCN-NEXT: v_mov_b32_e32 v0, s2
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; GCN-NEXT: global_store_dword v1, v0, s[0:1]
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; GCN-NEXT: s_endpgm
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entry: ; preds = %1009
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%0 = load i32, i32 addrspace(1)* %in, align 4
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%1 = load <4 x i32>, <4 x i32> addrspace(4)* %addrSrc, align 16
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%2 = icmp ne i32 %0, 0
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%3 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %1, i32 252, i32 0, i32 0)
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%4 = icmp ne i32 %3, 0
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%5 = xor i1 %2, %4
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%result = select i1 %5, i32 2, i32 3
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32 immarg)
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