5157f984ae
Currently not (xor_one_use) pattern is always selected to S_XNOR irrelative od the node divergence. This relies on further custom selection pass which converts to VALU if necessary and replaces with V_NOT_B32 ( V_XOR_B32) on those targets which have no V_XNOR. Current change enables the patterns which explicitly select the not (xor_one_use) to appropriate form. We assume that xor (not) is already turned into the not (xor) by the combiner. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D116270
45 lines
1.3 KiB
LLVM
45 lines
1.3 KiB
LLVM
; RUN: llc -march=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=gfx906 -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN_DL %s
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; GCN-LABEL: name: uniform_xnor_i64
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; GCN: S_XNOR_B64
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define amdgpu_kernel void @uniform_xnor_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%xor = xor i64 %a, %b
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%res = xor i64 %xor, -1
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store i64 %res, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: name: divergent_xnor_i64
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; GCN: V_XOR_B32_e64
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; GCN: V_XOR_B32_e64
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; GCN: V_NOT_B32_e32
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; GCN: V_NOT_B32_e32
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; GCN_DL: V_XNOR_B32_e64
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; GCN_DL: V_XNOR_B32_e64
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define i64 @divergent_xnor_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%xor = xor i64 %a, %b
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%res = xor i64 %xor, -1
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ret i64 %res
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}
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; GCN-LABEL: name: uniform_xnor_i32
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; GCN: S_XNOR_B32
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define amdgpu_kernel void @uniform_xnor_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%xor = xor i32 %a, %b
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%res = xor i32 %xor, -1
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: name: divergent_xnor_i32
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; GCN: V_XOR_B32_e64
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; GCN: V_NOT_B32_e32
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; GCN_DL: V_XNOR_B32_e64
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define i32 @divergent_xnor_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%xor = xor i32 %a, %b
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%res = xor i32 %xor, -1
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ret i32 %res
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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