da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
144 lines
5.5 KiB
LLVM
144 lines
5.5 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}fptoui_f16_to_i16
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_cvt_u32_f32_e32 v[[R_I16:[0-9]+]], v[[A_F32]]
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; VI: v_cvt_u16_f16_e32 v[[R_I16:[0-9]+]], v[[A_F16]]
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; GCN: buffer_store_short v[[R_I16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @fptoui_f16_to_i16(
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i16 addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = fptoui half %a.val to i16
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store i16 %r.val, i16 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fptoui_f16_to_i32
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; GCN: v_cvt_u32_f32_e32 v[[R_I32:[0-9]+]], v[[A_F32]]
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; GCN: buffer_store_dword v[[R_I32]]
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; GCN: s_endpgm
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define amdgpu_kernel void @fptoui_f16_to_i32(
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i32 addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = fptoui half %a.val to i32
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store i32 %r.val, i32 addrspace(1)* %r
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ret void
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}
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; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing
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; test checks code generated for 'i64 = fp_to_uint f32'.
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; GCN-LABEL: {{^}}fptoui_f16_to_i64
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: v_mov_b32_e32 v[[R_I64_High:[0-9]+]], 0
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; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; GCN: v_cvt_u32_f32_e32 v[[R_I64_Low:[0-9]+]], v[[A_F32]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[R_I64_Low]]{{\:}}[[R_I64_High]]{{\]}}
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; GCN: s_endpgm
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define amdgpu_kernel void @fptoui_f16_to_i64(
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i64 addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = fptoui half %a.val to i64
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store i64 %r.val, i64 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fptoui_v2f16_to_v2i16
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; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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; SI: v_cvt_u32_f32_e32 v[[R_I16_1:[0-9]+]], v[[A_F32_1]]
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; SI: v_cvt_u32_f32_e32 v[[R_I16_0:[0-9]+]], v[[A_F32_0]]
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; SI: v_lshlrev_b32_e32 v[[R_I16_HI:[0-9]+]], 16, v[[R_I16_1]]
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; SI: v_or_b32_e32 v[[R_V2_I16:[0-9]+]], v[[R_I16_0]], v[[R_I16_HI]]
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; VI: v_cvt_u16_f16_e32 v[[A_U16_1:[0-9]+]], v[[A_V2_F16]]
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; VI: v_cvt_u16_f16_sdwa v[[R_U16_0:[0-9]+]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
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; VI: v_or_b32_sdwa v[[R_V2_I16:[0-9]+]], v[[A_U16_1]], v[[R_U16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; GCN: buffer_store_dword v[[R_V2_I16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @fptoui_v2f16_to_v2i16(
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<2 x i16> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%r.val = fptoui <2 x half> %a.val to <2 x i16>
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store <2 x i16> %r.val, <2 x i16> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fptoui_v2f16_to_v2i32
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; GCN: buffer_load_dword
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; GCN: v_cvt_f32_f16_e32
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; SI: v_cvt_f32_f16_e32
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; VI: v_cvt_f32_f16_sdwa
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; GCN: v_cvt_u32_f32_e32
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; GCN: v_cvt_u32_f32_e32
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; GCN: buffer_store_dwordx2
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; GCN: s_endpgm
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define amdgpu_kernel void @fptoui_v2f16_to_v2i32(
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<2 x i32> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%r.val = fptoui <2 x half> %a.val to <2 x i32>
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store <2 x i32> %r.val, <2 x i32> addrspace(1)* %r
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ret void
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}
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; Need to make sure we promote f16 to f32 when converting f16 to i64. Existing
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; test checks code generated for 'i64 = fp_to_uint f32'.
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; GCN-LABEL: {{^}}fptoui_v2f16_to_v2i64
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; GCN: buffer_load_dword v[[A_F16_0:[0-9]+]]
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; GCN: v_mov_b32_e32 v[[R_I64_1_High:[0-9]+]], 0
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; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_F16_0]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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; SI: v_cvt_u32_f32_e32 v[[R_I64_0_Low:[0-9]+]], v[[A_F32_0]]
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; SI: v_cvt_u32_f32_e32 v[[R_I64_1_Low:[0-9]+]], v[[A_F32_1]]
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; VI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_F16_0]]
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; VI: v_cvt_f32_f16_sdwa v[[A_F32_1:[0-9]+]], v[[A_F16_0]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
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; VI: v_cvt_u32_f32_e32 v[[R_I64_0_Low:[0-9]+]], v[[A_F32_0]]
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; VI: v_cvt_u32_f32_e32 v[[R_I64_1_Low:[0-9]+]], v[[A_F32_1]]
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; GCN: v_mov_b32_e32 v[[R_I64_0_High:[0-9]+]], 0
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; GCN: buffer_store_dwordx4 v{{\[}}[[R_I64_0_Low]]{{\:}}[[R_I64_1_High]]{{\]}}
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; GCN: s_endpgm
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define amdgpu_kernel void @fptoui_v2f16_to_v2i64(
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<2 x i64> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%r.val = fptoui <2 x half> %a.val to <2 x i64>
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store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fptoui_f16_to_i1:
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; SI: v_cvt_f32_f16_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; SI: v_cmp_eq_f32_e32 vcc, 1.0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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; VI: v_cmp_eq_f16_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
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; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, s[4:5]
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define amdgpu_kernel void @fptoui_f16_to_i1(i1 addrspace(1)* %out, half %in) {
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entry:
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%conv = fptoui half %in to i1
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store i1 %conv, i1 addrspace(1)* %out
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ret void
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}
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