bd653f6406
Now AND is used for zero extension when both Zbb and Zbp are not enabled. It may be better to use shift operation if the trailing ones mask exceeds simm12. This patch optimzes LUI+ADDI+AND to SLLI+SRLI. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D116720
73 lines
1.8 KiB
LLVM
73 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; Test for handling of AND with constant. If this constant exceeds simm12 and
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; also is a non-empty sequence of ones starting at the least significant bit
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; with the remainder zero, we can replace it with SLLI + SLRI
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define i32 @and32_0x7ff(i32 %x) {
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; RV32I-LABEL: and32_0x7ff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 2047
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and32_0x7ff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 2047
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; RV64I-NEXT: ret
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%a = and i32 %x, 2047
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ret i32 %a
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}
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define i32 @and32_0xfff(i32 %x) {
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; RV32I-LABEL: and32_0xfff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 20
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; RV32I-NEXT: srli a0, a0, 20
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and32_0xfff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: srli a0, a0, 52
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; RV64I-NEXT: ret
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%a = and i32 %x, 4095
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ret i32 %a
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}
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define i64 @and64_0x7ff(i64 %x) {
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; RV32I-LABEL: and64_0x7ff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 2047
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0x7ff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 2047
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; RV64I-NEXT: ret
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%a = and i64 %x, 2047
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ret i64 %a
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}
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define i64 @and64_0xfff(i64 %x) {
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; RV32I-LABEL: and64_0xfff:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 20
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; RV32I-NEXT: srli a0, a0, 20
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and64_0xfff:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: srli a0, a0, 52
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; RV64I-NEXT: ret
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%a = and i64 %x, 4095
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ret i64 %a
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}
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