efd4938723
This patch tries to use an existing VPWidenCanonicalIVRecipe
instead of creating another step-vector for canonical
induction recipes in widenIntOrFpInduction.
This has the following benefits:
1. First step to avoid setting both vector and scalar values for the
same induction def.
2. Reducing complexity of widenIntOrFpInduction through making things
more explicit in VPlan
3. Only need to splat the vector IV for block in masks.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D116123
89 lines
4.7 KiB
LLVM
89 lines
4.7 KiB
LLVM
; RUN: opt -loop-vectorize -scalable-vectorization=off -force-vector-width=4 -prefer-predicate-over-epilogue=predicate-dont-vectorize -S < %s | FileCheck %s
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; NOTE: These tests aren't really target-specific, but it's convenient to target AArch64
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; so that TTI.isLegalMaskedLoad can return true.
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target triple = "aarch64-linux-gnu"
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; The original loop had an unconditional uniform load. Let's make sure
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; we don't artificially create new predicated blocks for the load.
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define void @uniform_load(i32* noalias %dst, i32* noalias readonly %src, i64 %n) #0 {
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; CHECK-LABEL: @uniform_load(
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; CHECK: vector.body:
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; CHECK-NEXT: [[IDX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[IDX_NEXT:%.*]], %vector.body ]
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; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[IDX]], 0
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; CHECK-NEXT: [[LOOP_PRED:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[TMP3]], i64 %n)
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; CHECK-NEXT: [[LOAD_VAL:%.*]] = load i32, i32* %src, align 4
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; CHECK-NOT: load i32, i32* %src, align 4
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> poison, i32 [[LOAD_VAL]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, i32* %dst, i64 [[TMP3]]
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[TMP6]], i32 0
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; CHECK-NEXT: [[STORE_PTR:%.*]] = bitcast i32* [[TMP7]] to <4 x i32>*
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; CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[TMP5]], <4 x i32>* [[STORE_PTR]], i32 4, <4 x i1> [[LOOP_PRED]])
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; CHECK-NEXT: [[IDX_NEXT]] = add i64 [[IDX]], 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[IDX_NEXT]], %n.vec
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; CHECK-NEXT: br i1 [[CMP]], label %middle.block, label %vector.body
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%val = load i32, i32* %src, align 4
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%arrayidx = getelementptr inbounds i32, i32* %dst, i64 %indvars.iv
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store i32 %val, i32* %arrayidx, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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; The original loop had a conditional uniform load. In this case we actually
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; do need to perform conditional loads and so we end up using a gather instead.
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; However, we at least ensure the mask is the overlap of the loop predicate
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; and the original condition.
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define void @cond_uniform_load(i32* nocapture %dst, i32* nocapture readonly %src, i32* nocapture readonly %cond, i64 %n) #0 {
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; CHECK-LABEL: @cond_uniform_load(
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; CHECK: vector.ph:
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; CHECK: [[TMP1:%.*]] = insertelement <4 x i32*> poison, i32* %src, i32 0
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; CHECK-NEXT: [[SRC_SPLAT:%.*]] = shufflevector <4 x i32*> [[TMP1]], <4 x i32*> poison, <4 x i32> zeroinitializer
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; CHECK: vector.body:
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; CHECK-NEXT: [[IDX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[IDX_NEXT:%.*]], %vector.body ]
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; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[IDX]], 0
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; CHECK-NEXT: [[LOOP_PRED:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[TMP3]], i64 %n)
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; CHECK: [[COND_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* {{%.*}}, i32 4, <4 x i1> [[LOOP_PRED]], <4 x i32> poison)
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x i32> [[COND_LOAD]], zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = xor <4 x i1> [[TMP4]], <i1 true, i1 true, i1 true, i1 true>
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; CHECK-NEXT: [[MASK:%.*]] = select <4 x i1> [[LOOP_PRED]], <4 x i1> [[TMP5]], <4 x i1> zeroinitializer
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; CHECK-NEXT: call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[SRC_SPLAT]], i32 4, <4 x i1> [[MASK]], <4 x i32> undef)
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entry:
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br label %for.body
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for.body: ; preds = %entry, %if.end
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%index = phi i64 [ %index.next, %if.end ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %cond, i64 %index
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%0 = load i32, i32* %arrayidx, align 4
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%tobool.not = icmp eq i32 %0, 0
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br i1 %tobool.not, label %if.end, label %if.then
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if.then: ; preds = %for.body
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%1 = load i32, i32* %src, align 4
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br label %if.end
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if.end: ; preds = %if.then, %for.body
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%val.0 = phi i32 [ %1, %if.then ], [ 0, %for.body ]
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%arrayidx1 = getelementptr inbounds i32, i32* %dst, i64 %index
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store i32 %val.0, i32* %arrayidx1, align 4
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%index.next = add nuw i64 %index, 1
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%exitcond.not = icmp eq i64 %index.next, %n
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br i1 %exitcond.not, label %for.end, label %for.body
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for.end: ; preds = %for.inc, %entry
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ret void
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}
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attributes #0 = { "target-features"="+neon,+sve,+v8.1a" vscale_range(2, 0) }
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