2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
280 lines
10 KiB
C++
280 lines
10 KiB
C++
//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Mips specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsSubtarget.h"
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#include "Mips.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsCallLowering.h"
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#include "MipsLegalizerInfo.h"
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#include "MipsRegisterBankInfo.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "MipsGenSubtargetInfo.inc"
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// FIXME: Maybe this should be on by default when Mips16 is specified
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//
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static cl::opt<bool>
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Mixed16_32("mips-mixed-16-32", cl::init(false),
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cl::desc("Allow for a mixture of Mips16 "
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"and Mips32 code in a single output file"),
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cl::Hidden);
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static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
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cl::desc("Compile all functions that don't use "
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"floating point as Mips 16"),
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cl::Hidden);
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static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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cl::desc("Enable mips16 hard float."),
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cl::init(false));
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static cl::opt<bool>
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Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
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cl::desc("Enable mips16 constant islands."),
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cl::init(true));
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static cl::opt<bool>
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GPOpt("mgpopt", cl::Hidden,
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cl::desc("Enable gp-relative addressing of mips small data items"));
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bool MipsSubtarget::DspWarningPrinted = false;
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bool MipsSubtarget::MSAWarningPrinted = false;
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bool MipsSubtarget::VirtWarningPrinted = false;
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bool MipsSubtarget::CRCWarningPrinted = false;
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bool MipsSubtarget::GINVWarningPrinted = false;
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void MipsSubtarget::anchor() {}
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MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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bool little, const MipsTargetMachine &TM,
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unsigned StackAlignOverride)
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: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
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IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
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NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
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IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
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HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
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HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
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InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
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HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
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Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
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HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
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HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
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StackAlignOverride(StackAlignOverride),
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TM(TM), TargetTriple(TT), TSInfo(),
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InstrInfo(
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MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
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FrameLowering(MipsFrameLowering::create(*this)),
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TLInfo(MipsTargetLowering::create(TM, *this)) {
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if (MipsArchVersion == MipsDefault)
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MipsArchVersion = Mips32;
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// Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
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// been tested and currently exist for the integrated assembler only.
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if (MipsArchVersion == Mips1)
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report_fatal_error("Code generation for MIPS-I is not implemented", false);
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if (MipsArchVersion == Mips5)
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report_fatal_error("Code generation for MIPS-V is not implemented", false);
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// Check if Architecture and ABI are compatible.
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assert(((!isGP64bit() && isABI_O32()) ||
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(isGP64bit() && (isABI_N32() || isABI_N64()))) &&
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"Invalid Arch & ABI pair.");
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if (hasMSA() && !isFP64bit())
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report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
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"See -mattr=+fp64.",
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false);
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if (!isABI_O32() && !useOddSPReg())
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report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
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if (IsFPXX && (isABI_N32() || isABI_N64()))
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report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
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if (hasMips64r6() && InMicroMipsMode)
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report_fatal_error("microMIPS64R6 is not supported", false);
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if (!isABI_O32() && InMicroMipsMode)
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report_fatal_error("microMIPS64 is not supported.", false);
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if (UseIndirectJumpsHazard) {
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if (InMicroMipsMode)
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report_fatal_error(
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"cannot combine indirect jumps with hazard barriers and microMIPS");
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if (!hasMips32r2())
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report_fatal_error(
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"indirect jumps with hazard barriers requires MIPS32R2 or later");
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}
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if (hasMips32r6()) {
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StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
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assert(isFP64bit());
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assert(isNaN2008());
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if (hasDSP())
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report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
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}
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if (NoABICalls && TM.isPositionIndependent())
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report_fatal_error("position-independent code requires '-mabicalls'");
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if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
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NoABICalls = true;
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// Set UseSmallSection.
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UseSmallSection = GPOpt;
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if (!NoABICalls && GPOpt) {
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errs() << "warning: cannot use small-data accesses for '-mabicalls'"
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<< "\n";
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UseSmallSection = false;
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}
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if (hasDSPR2() && !DspWarningPrinted) {
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if (hasMips64() && !hasMips64r2()) {
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errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
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<< "greater\n";
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DspWarningPrinted = true;
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} else if (hasMips32() && !hasMips32r2()) {
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errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
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<< "greater\n";
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DspWarningPrinted = true;
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}
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} else if (hasDSP() && !DspWarningPrinted) {
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if (hasMips64() && !hasMips64r2()) {
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errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
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<< "greater\n";
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DspWarningPrinted = true;
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} else if (hasMips32() && !hasMips32r2()) {
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errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
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<< "greater\n";
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DspWarningPrinted = true;
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}
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}
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StringRef ArchName = hasMips64() ? "MIPS64" : "MIPS32";
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if (!hasMips32r5() && hasMSA() && !MSAWarningPrinted) {
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errs() << "warning: the 'msa' ASE requires " << ArchName
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<< " revision 5 or greater\n";
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MSAWarningPrinted = true;
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}
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if (!hasMips32r5() && hasVirt() && !VirtWarningPrinted) {
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errs() << "warning: the 'virt' ASE requires " << ArchName
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<< " revision 5 or greater\n";
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VirtWarningPrinted = true;
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}
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if (!hasMips32r6() && hasCRC() && !CRCWarningPrinted) {
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errs() << "warning: the 'crc' ASE requires " << ArchName
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<< " revision 6 or greater\n";
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CRCWarningPrinted = true;
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}
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if (!hasMips32r6() && hasGINV() && !GINVWarningPrinted) {
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errs() << "warning: the 'ginv' ASE requires " << ArchName
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<< " revision 6 or greater\n";
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GINVWarningPrinted = true;
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}
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CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering()));
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Legalizer.reset(new MipsLegalizerInfo(*this));
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auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo());
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RegBankInfo.reset(RBI);
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InstSelector.reset(createMipsInstructionSelector(
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*static_cast<const MipsTargetMachine *>(&TM), *this, *RBI));
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}
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bool MipsSubtarget::isPositionIndependent() const {
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return TM.isPositionIndependent();
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}
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/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
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bool MipsSubtarget::enablePostRAScheduler() const { return true; }
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void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
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: &Mips::GPR32RegClass);
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}
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CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
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return CodeGenOpt::Aggressive;
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}
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MipsSubtarget &
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MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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const TargetMachine &TM) {
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std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FS);
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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if (InMips16Mode && !IsSoftFloat)
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InMips16HardFloat = true;
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if (StackAlignOverride)
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stackAlignment = StackAlignOverride;
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else if (isABI_N32() || isABI_N64())
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stackAlignment = 16;
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else {
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assert(isABI_O32() && "Unknown ABI for stack alignment!");
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stackAlignment = 8;
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}
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return *this;
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}
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bool MipsSubtarget::useConstantIslands() {
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LLVM_DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands
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<< "\n");
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return Mips16ConstantIslands;
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}
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Reloc::Model MipsSubtarget::getRelocationModel() const {
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return TM.getRelocationModel();
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}
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bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
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bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
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bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
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const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
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const CallLowering *MipsSubtarget::getCallLowering() const {
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return CallLoweringInfo.get();
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}
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const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const {
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return Legalizer.get();
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}
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const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const {
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return RegBankInfo.get();
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}
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const InstructionSelector *MipsSubtarget::getInstructionSelector() const {
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return InstSelector.get();
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}
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