f24ec7bdd0
When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
119 lines
3.9 KiB
LLVM
119 lines
3.9 KiB
LLVM
; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
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define void @test_liwzx1(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
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; P9LE-LABEL: test_liwzx1:
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; P9LE: # %bb.0:
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; P9LE-NEXT: lfiwzx f0, 0, r3
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; P9LE-NEXT: lfiwzx f1, 0, r4
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; P9LE-NEXT: xxpermdi vs0, f0, f0, 2
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; P9LE-NEXT: xxpermdi vs1, f1, f1, 2
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; P9LE-NEXT: xvaddsp vs0, vs0, vs1
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; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 3
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; P9LE-NEXT: xscvspdpn f0, vs0
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; P9LE-NEXT: stfs f0, 0(r5)
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; P9LE-NEXT: blr
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; P9BE-LABEL: test_liwzx1:
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; P9BE: # %bb.0:
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; P9BE-NEXT: lfiwzx f0, 0, r3
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; P9BE-NEXT: lfiwzx f1, 0, r4
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; P9BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P9BE-NEXT: xxsldwi vs1, f1, f1, 1
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; P9BE-NEXT: xvaddsp vs0, vs0, vs1
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; P9BE-NEXT: xscvspdpn f0, vs0
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; P9BE-NEXT: stfs f0, 0(r5)
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; P9BE-NEXT: blr
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; P8LE-LABEL: test_liwzx1:
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; P8LE: # %bb.0:
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; P8LE-NEXT: lfiwzx f0, 0, r3
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; P8LE-NEXT: lfiwzx f1, 0, r4
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; P8LE-NEXT: xxpermdi vs0, f0, f0, 2
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; P8LE-NEXT: xxpermdi vs1, f1, f1, 2
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; P8LE-NEXT: xvaddsp vs0, vs0, vs1
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; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 3
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; P8LE-NEXT: xscvspdpn f0, vs0
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; P8LE-NEXT: stfsx f0, 0, r5
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; P8LE-NEXT: blr
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; P8BE-LABEL: test_liwzx1:
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; P8BE: # %bb.0:
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; P8BE-NEXT: lfiwzx f0, 0, r3
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; P8BE-NEXT: lfiwzx f1, 0, r4
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE-NEXT: xxsldwi vs1, f1, f1, 1
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; P8BE-NEXT: xvaddsp vs0, vs0, vs1
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; P8BE-NEXT: xscvspdpn f0, vs0
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; P8BE-NEXT: stfsx f0, 0, r5
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; P8BE-NEXT: blr
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%a = load <1 x float>, <1 x float>* %A
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%b = load <1 x float>, <1 x float>* %B
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%X = fadd <1 x float> %a, %b
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store <1 x float> %X, <1 x float>* %C
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ret void
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}
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define <1 x float>* @test_liwzx2(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
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; P9LE-LABEL: test_liwzx2:
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; P9LE: # %bb.0:
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; P9LE-NEXT: lfiwzx f0, 0, r3
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; P9LE-NEXT: lfiwzx f1, 0, r4
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; P9LE-NEXT: xxpermdi vs0, f0, f0, 2
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; P9LE-NEXT: xxpermdi vs1, f1, f1, 2
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; P9LE-NEXT: xvsubsp vs0, vs0, vs1
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; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 3
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; P9LE-NEXT: xscvspdpn f0, vs0
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; P9LE-NEXT: mr r3, r5
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; P9LE-NEXT: stfs f0, 0(r5)
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; P9LE-NEXT: blr
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; P9BE-LABEL: test_liwzx2:
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; P9BE: # %bb.0:
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; P9BE-NEXT: lfiwzx f0, 0, r3
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; P9BE-NEXT: lfiwzx f1, 0, r4
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; P9BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P9BE-NEXT: xxsldwi vs1, f1, f1, 1
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; P9BE-NEXT: xvsubsp vs0, vs0, vs1
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; P9BE-NEXT: xscvspdpn f0, vs0
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; P9BE-NEXT: mr r3, r5
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; P9BE-NEXT: stfs f0, 0(r5)
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; P9BE-NEXT: blr
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; P8LE-LABEL: test_liwzx2:
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; P8LE: # %bb.0:
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; P8LE-NEXT: lfiwzx f0, 0, r3
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; P8LE-NEXT: lfiwzx f1, 0, r4
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; P8LE-NEXT: mr r3, r5
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; P8LE-NEXT: xxpermdi vs0, f0, f0, 2
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; P8LE-NEXT: xxpermdi vs1, f1, f1, 2
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; P8LE-NEXT: xvsubsp vs0, vs0, vs1
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; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 3
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; P8LE-NEXT: xscvspdpn f0, vs0
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; P8LE-NEXT: stfsx f0, 0, r5
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; P8LE-NEXT: blr
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; P8BE-LABEL: test_liwzx2:
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; P8BE: # %bb.0:
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; P8BE-NEXT: lfiwzx f0, 0, r3
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; P8BE-NEXT: lfiwzx f1, 0, r4
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; P8BE-NEXT: mr r3, r5
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE-NEXT: xxsldwi vs1, f1, f1, 1
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; P8BE-NEXT: xvsubsp vs0, vs0, vs1
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; P8BE-NEXT: xscvspdpn f0, vs0
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; P8BE-NEXT: stfsx f0, 0, r5
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; P8BE-NEXT: blr
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%a = load <1 x float>, <1 x float>* %A
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%b = load <1 x float>, <1 x float>* %B
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%X = fsub <1 x float> %a, %b
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store <1 x float> %X, <1 x float>* %C
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ret <1 x float>* %C
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}
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