0c64e1b68f
When adding pcsections to SDNodes, recursively add them to all values of the node as well. Reviewed By: melver Differential Revision: https://reviews.llvm.org/D141048
181 lines
5.2 KiB
LLVM
181 lines
5.2 KiB
LLVM
; RUN: llc -O0 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
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; RUN: llc -O1 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
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; RUN: llc -O2 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
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; RUN: llc -O3 < %s | FileCheck %s --check-prefixes=CHECK,DEFCM
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; RUN: llc -O1 -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE
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target triple = "x86_64-unknown-linux-gnu"
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@foo = dso_local global i64 0, align 8
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@bar = dso_local global i64 0, align 8
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define void @empty_no_aux() !pcsections !0 {
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; CHECK-LABEL: empty_no_aux:
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; CHECK-NEXT: .Lfunc_begin0
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: retq
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; CHECK-NEXT: .Lfunc_end0:
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; CHECK: .section section_no_aux,"awo",@progbits,.text
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; CHECK-NEXT: .Lpcsection_base0:
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; DEFCM-NEXT: .long .Lfunc_begin0-.Lpcsection_base0
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; LARGE-NEXT: .quad .Lfunc_begin0-.Lpcsection_base0
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; CHECK-NEXT: .long .Lfunc_end0-.Lfunc_begin0
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; CHECK-NEXT: .text
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entry:
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ret void
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}
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define void @empty_aux() !pcsections !1 {
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; CHECK-LABEL: empty_aux:
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; CHECK-NEXT: .Lfunc_begin1
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: retq
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; CHECK-NEXT: .Lfunc_end1:
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; CHECK: .section section_aux,"awo",@progbits,.text
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; CHECK-NEXT: .Lpcsection_base1:
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; DEFCM-NEXT: .long .Lfunc_begin1-.Lpcsection_base1
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; LARGE-NEXT: .quad .Lfunc_begin1-.Lpcsection_base1
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; CHECK-NEXT: .long .Lfunc_end1-.Lfunc_begin1
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; CHECK-NEXT: .long 10
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; CHECK-NEXT: .long 20
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; CHECK-NEXT: .long 30
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; CHECK-NEXT: .text
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entry:
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ret void
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}
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define i64 @multiple() !pcsections !0 {
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; CHECK-LABEL: multiple:
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; CHECK-NEXT: .Lfunc_begin2
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; CHECK: # %bb.0: # %entry
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; --
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; DEFCM: .Lpcsection0:
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; DEFCM-NEXT: movq
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; --
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; LARGE: .Lpcsection0:
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; LARGE-NEXT: movabsq
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; LARGE-NEXT: .Lpcsection1:
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; LARGE-NEXT: movq
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; --
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; CHECK-NEXT: retq
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; CHECK-NEXT: .Lfunc_end2:
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; CHECK: .section section_no_aux,"awo",@progbits,.text
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; --
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; DEFCM-NEXT: .Lpcsection_base2:
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; DEFCM-NEXT: .long .Lfunc_begin2-.Lpcsection_base2
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; DEFCM-NEXT: .long .Lfunc_end2-.Lfunc_begin2
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; DEFCM-NEXT: .section section_aux_42,"awo",@progbits,.text
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; DEFCM-NEXT: .Lpcsection_base3:
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; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base3
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; DEFCM-NEXT: .long 42
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; DEFCM-NEXT: .section section_aux_21264,"awo",@progbits,.text
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; DEFCM-NEXT: .Lpcsection_base4:
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; DEFCM-NEXT: .long .Lpcsection0-.Lpcsection_base4
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; DEFCM-NEXT: .long 21264
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; --
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; LARGE: .Lpcsection_base2:
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; LARGE-NEXT: .quad .Lfunc_begin2-.Lpcsection_base2
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; LARGE-NEXT: .long .Lfunc_end2-.Lfunc_begin2
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; LARGE-NEXT: .section section_aux_42,"awo",@progbits,.text
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; LARGE-NEXT: .Lpcsection_base3:
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; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base3
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; LARGE-NEXT: .Lpcsection_base4:
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; LARGE-NEXT: .quad .Lpcsection1-.Lpcsection_base4
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; LARGE-NEXT: .long 42
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; LARGE-NEXT: .section section_aux_21264,"awo",@progbits,.text
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; LARGE-NEXT: .Lpcsection_base5:
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; LARGE-NEXT: .quad .Lpcsection0-.Lpcsection_base5
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; LARGE-NEXT: .Lpcsection_base6:
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; LARGE-NEXT: .quad .Lpcsection1-.Lpcsection_base6
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; LARGE-NEXT: .long 21264
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; --
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; CHECK-NEXT: .text
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entry:
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%0 = load i64, ptr @bar, align 8, !pcsections !2
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ret i64 %0
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}
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define i64 @test_simple_atomic() {
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; CHECK-LABEL: test_simple_atomic:
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; --
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; DEFCM: .Lpcsection1:
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; DEFCM-NEXT: movq
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; --
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; LARGE: .Lpcsection2:
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; LARGE-NEXT: movabsq
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; LARGE-NEXT: .Lpcsection3:
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; LARGE-NEXT: movq
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; --
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; CHECK-NOT: .Lpcsection
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; CHECK: addq
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; CHECK-NEXT: retq
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; CHECK-NEXT: .Lfunc_end3:
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; CHECK: .section section_no_aux,"awo",@progbits,.text
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; --
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; DEFCM-NEXT: .Lpcsection_base5:
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; DEFCM-NEXT: .long .Lpcsection1-.Lpcsection_base5
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; --
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; LARGE-NEXT: .Lpcsection_base7:
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; LARGE-NEXT: .quad .Lpcsection2-.Lpcsection_base7
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; LARGE-NEXT: .Lpcsection_base8:
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; LARGE-NEXT: .quad .Lpcsection3-.Lpcsection_base8
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; --
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; CHECK-NEXT: .text
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entry:
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%0 = load atomic i64, ptr @foo monotonic, align 8, !pcsections !0
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%1 = load i64, ptr @bar, align 8
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%add = add nsw i64 %1, %0
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ret i64 %add
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}
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define i64 @test_complex_atomic() {
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; CHECK-LABEL: test_complex_atomic:
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; --
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; DEFCM: .Lpcsection2:
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; DEFCM-NEXT: movl
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; DEFCM-NEXT: .Lpcsection3:
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; DEFCM-NEXT: lock
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; --
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; LARGE: .Lpcsection4:
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; LARGE-NEXT: movabsq
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; LARGE-NEXT: .Lpcsection5:
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; LARGE-NEXT: movl
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; LARGE-NEXT: .Lpcsection6:
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; LARGE-NEXT: lock
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; --
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; CHECK-NOT: .Lpcsection
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; CHECK: movq
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; CHECK: addq
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; CHECK: retq
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; CHECK-NEXT: .Lfunc_end4:
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; CHECK: .section section_no_aux,"awo",@progbits,.text
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; --
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; DEFCM-NEXT: .Lpcsection_base6:
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; DEFCM-NEXT: .long .Lpcsection2-.Lpcsection_base6
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; DEFCM-NEXT: .Lpcsection_base7:
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; DEFCM-NEXT: .long .Lpcsection3-.Lpcsection_base7
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; --
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; LARGE-NEXT: .Lpcsection_base9:
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; LARGE-NEXT: .quad .Lpcsection4-.Lpcsection_base9
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; LARGE-NEXT: .Lpcsection_base10:
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; LARGE-NEXT: .quad .Lpcsection5-.Lpcsection_base10
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; LARGE-NEXT: .Lpcsection_base11:
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; LARGE-NEXT: .quad .Lpcsection6-.Lpcsection_base11
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; --
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; CHECK-NEXT: .text
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entry:
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%0 = atomicrmw add ptr @foo, i64 1 monotonic, align 8, !pcsections !0
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%1 = load i64, ptr @bar, align 8
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%inc = add nsw i64 %1, 1
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store i64 %inc, ptr @bar, align 8
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%add = add nsw i64 %1, %0
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ret i64 %add
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}
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!0 = !{!"section_no_aux"}
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!1 = !{!"section_aux", !3}
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!2 = !{!"section_aux_42", !4, !"section_aux_21264", !5}
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!3 = !{i32 10, i32 20, i32 30}
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!4 = !{i32 42}
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!5 = !{i32 21264}
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