This patch adds the logic necessary to target the sparse-tensor dialect integration tests for SVE. As the LLVM backend for AArch64 does not currently support product reductions, the corresponding tests are disabled for SVE. Not all tests have been updated yet. The remaining tests will be refactored in a separate patch shortly. Differential Revision: https://reviews.llvm.org/D121304 Co-authored-by: Andrzej Warzynski <andrzej.warzynski@arm.com>
117 lines
4.4 KiB
MLIR
117 lines
4.4 KiB
MLIR
// DEFINE: %{option} = enable-runtime-library=true
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// DEFINE: %{compile} = mlir-opt %s --sparse-compiler=%{option}
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// DEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/test.tns" \
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// DEFINE: mlir-cpu-runner \
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// DEFINE: -e entry -entry-point-result=void \
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// DEFINE: -shared-libs=%mlir_lib_dir/libmlir_c_runner_utils%shlibext,%mlir_lib_dir/libmlir_runner_utils%shlibext | \
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// DEFINE: FileCheck %s
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//
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// RUN: %{compile} | %{run}
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//
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// Do the same run, but now with direct IR generation.
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// REDEFINE: %{option} = enable-runtime-library=false
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// RUN: %{compile} | %{run}
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//
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// Do the same run, but now with direct IR generation and vectorization.
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// REDEFINE: %{option} = "enable-runtime-library=false vl=2 reassociate-fp-reductions=true enable-index-optimizations=true"
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// RUN: %{compile} | %{run}
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// If SVE is available, do the same run, but now with direct IR generation and VLA
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// vectorization.
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// REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA"
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// REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/test.tns" \
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// REDEFINE: %lli \
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// REDEFINE: --entry-function=entry_lli \
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// REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \
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// REDEFINE: %VLA_ARCH_ATTR_OPTIONS \
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// REDEFINE: --dlopen=%mlir_native_utils_lib_dir/libmlir_c_runner_utils%shlibext --dlopen=%mlir_lib_dir/libmlir_runner_utils%shlibext | \
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// REDEFINE: FileCheck %s
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// RUN: %{compile} | mlir-translate -mlir-to-llvmir | %{run}
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!Filename = !llvm.ptr<i8>
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#SparseTensor = #sparse_tensor.encoding<{
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dimLevelType = [ "compressed", "compressed", "compressed", "compressed",
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"compressed", "compressed", "compressed", "compressed" ],
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// Note that any dimOrdering permutation should give the same results
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// since, even though it impacts the sparse storage scheme layout,
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// it should not change the semantics.
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dimOrdering = affine_map<(i,j,k,l,m,n,o,p) -> (p,o,j,k,i,l,m,n)>
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}>
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#trait_flatten = {
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indexing_maps = [
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affine_map<(i,j,k,l,m,n,o,p) -> (i,j,k,l,m,n,o,p)>, // A
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affine_map<(i,j,k,l,m,n,o,p) -> (i,j)> // X (out)
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],
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iterator_types = [ "parallel", "parallel", "reduction", "reduction",
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"reduction", "reduction", "reduction", "reduction" ],
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doc = "X(i,j) += A(i,j,k,l,m,n,o,p)"
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}
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//
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// Integration test that lowers a kernel annotated as sparse to
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// actual sparse code, initializes a matching sparse storage scheme
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// from file, and runs the resulting code with the JIT compiler.
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//
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module {
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//
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// A kernel that flattens a rank 8 tensor into a dense matrix.
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//
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func.func @kernel_flatten(%arga: tensor<7x3x3x3x3x3x5x3xf64, #SparseTensor>,
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%argx: tensor<7x3xf64>)
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-> tensor<7x3xf64> {
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%0 = linalg.generic #trait_flatten
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ins(%arga: tensor<7x3x3x3x3x3x5x3xf64, #SparseTensor>)
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outs(%argx: tensor<7x3xf64>) {
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^bb(%a: f64, %x: f64):
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%0 = arith.addf %x, %a : f64
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linalg.yield %0 : f64
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} -> tensor<7x3xf64>
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return %0 : tensor<7x3xf64>
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}
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func.func private @getTensorFilename(index) -> (!Filename)
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func.func private @printMemrefF64(%ptr : tensor<*xf64>)
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//
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// Main driver that reads tensor from file and calls the sparse kernel.
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//
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func.func @entry() {
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%d0 = arith.constant 0.0 : f64
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%c0 = arith.constant 0 : index
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%c1 = arith.constant 1 : index
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%c3 = arith.constant 3 : index
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%c7 = arith.constant 7 : index
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// Setup matrix memory that is initialized to zero.
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%x = arith.constant dense<0.000000e+00> : tensor<7x3xf64>
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// Read the sparse tensor from file, construct sparse storage.
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%fileName = call @getTensorFilename(%c0) : (index) -> (!Filename)
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%a = sparse_tensor.new %fileName : !Filename to tensor<7x3x3x3x3x3x5x3xf64, #SparseTensor>
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// Call the kernel.
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%0 = call @kernel_flatten(%a, %x)
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: (tensor<7x3x3x3x3x3x5x3xf64, #SparseTensor>, tensor<7x3xf64>) -> tensor<7x3xf64>
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// Print the result for verification.
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//
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// CHECK: {{\[}}[6.25, 0, 0],
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// CHECK-NEXT: [4.224, 6.21, 0],
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// CHECK-NEXT: [0, 0, 15.455],
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// CHECK-NEXT: [0, 0, 0],
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// CHECK-NEXT: [0, 0, 0],
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// CHECK-NEXT: [0, 0, 0],
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// CHECK-NEXT: [7, 0, 0]]
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//
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%1 = tensor.cast %0 : tensor<7x3xf64> to tensor<*xf64>
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call @printMemrefF64(%1) : (tensor<*xf64>) -> ()
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// Release the resources.
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bufferization.dealloc_tensor %a : tensor<7x3x3x3x3x3x5x3xf64, #SparseTensor>
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return
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}
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}
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