9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
87 lines
3.6 KiB
LLVM
87 lines
3.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_11 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9_11 %s
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; GCN-LABEL: flat_inst_offset:
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; GFX9_11: flat_load_{{dword|b32}} v{{[0-9]+}}, v[{{[0-9:]+}}] offset:4
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; GFX9_11: flat_store_{{dword|b32}} v[{{[0-9:]+}}], v{{[0-9]+}} offset:4
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; GFX10: flat_load_dword v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
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; GFX10: flat_store_dword v[{{[0-9:]+}}], v{{[0-9]+}}{{$}}
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define void @flat_inst_offset(ptr nocapture %p) {
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%gep = getelementptr inbounds i32, ptr %p, i64 1
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%load = load i32, ptr %gep, align 4
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%inc = add nsw i32 %load, 1
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store i32 %inc, ptr %gep, align 4
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ret void
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}
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; GCN-LABEL: global_inst_offset:
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; GCN: global_load_{{dword|b32}} v{{[0-9]+}}, v[{{[0-9:]+}}], off offset:4
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; GCN: global_store_{{dword|b32}} v[{{[0-9:]+}}], v{{[0-9]+}}, off offset:4
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define void @global_inst_offset(ptr addrspace(1) nocapture %p) {
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%gep = getelementptr inbounds i32, ptr addrspace(1) %p, i64 1
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%load = load i32, ptr addrspace(1) %gep, align 4
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%inc = add nsw i32 %load, 1
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store i32 %inc, ptr addrspace(1) %gep, align 4
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ret void
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}
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; GCN-LABEL: load_i16_lo:
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; GFX9_11: flat_load_{{short_d16|d16_b16}} v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
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; GFX10: flat_load_short_d16 v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
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define amdgpu_kernel void @load_i16_lo(ptr %arg, ptr %out) {
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%gep = getelementptr inbounds i16, ptr %arg, i32 4
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%ld = load i16, ptr %gep, align 2
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%vec = insertelement <2 x i16> <i16 undef, i16 0>, i16 %ld, i32 0
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%v = add <2 x i16> %vec, %vec
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store <2 x i16> %v, ptr %out, align 4
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ret void
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}
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; GCN-LABEL: load_i16_hi:
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; GFX9_11: flat_load_{{short_d16_hi|d16_hi_b16}} v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
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; GFX10: flat_load_short_d16_hi v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
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define amdgpu_kernel void @load_i16_hi(ptr %arg, ptr %out) {
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%gep = getelementptr inbounds i16, ptr %arg, i32 4
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%ld = load i16, ptr %gep, align 2
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%vec = insertelement <2 x i16> <i16 0, i16 undef>, i16 %ld, i32 1
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%v = add <2 x i16> %vec, %vec
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store <2 x i16> %v, ptr %out, align 4
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ret void
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}
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; GCN-LABEL: load_half_lo:
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; GFX9_11: flat_load_{{short_d16|d16_b16}} v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
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; GFX10: flat_load_short_d16 v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
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define amdgpu_kernel void @load_half_lo(ptr %arg, ptr %out) {
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%gep = getelementptr inbounds half, ptr %arg, i32 4
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%ld = load half, ptr %gep, align 2
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%vec = insertelement <2 x half> <half undef, half 0xH0000>, half %ld, i32 0
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%v = fadd <2 x half> %vec, %vec
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store <2 x half> %v, ptr %out, align 4
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ret void
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}
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; GCN-LABEL: load_half_hi:
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; GFX9_11: flat_load_{{short_d16_hi|d16_hi_b16}} v{{[0-9]+}}, v[{{[0-9:]+}}] offset:8{{$}}
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; GFX10: flat_load_short_d16_hi v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
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define amdgpu_kernel void @load_half_hi(ptr %arg, ptr %out) {
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%gep = getelementptr inbounds half, ptr %arg, i32 4
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%ld = load half, ptr %gep, align 2
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%vec = insertelement <2 x half> <half 0xH0000, half undef>, half %ld, i32 1
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%v = fadd <2 x half> %vec, %vec
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store <2 x half> %v, ptr %out, align 4
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ret void
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}
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; GCN-LABEL: load_float_lo:
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; GFX9_11: flat_load_{{dword|b32}} v{{[0-9]+}}, v[{{[0-9:]+}}] offset:16{{$}}
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; GFX10: flat_load_dword v{{[0-9]+}}, v[{{[0-9:]+}}]{{$}}
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define amdgpu_kernel void @load_float_lo(ptr %arg, ptr %out) {
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%gep = getelementptr inbounds float, ptr %arg, i32 4
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%ld = load float, ptr %gep, align 4
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%v = fadd float %ld, %ld
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store float %v, ptr %out, align 4
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ret void
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}
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