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c6ac2e1e80098594620cb7d60c1c6552bbb2d49a
clang-p2996/llvm/test/CodeGen/MIR
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Matt Arsenault 44540a3db2 PeepholeOptimizer: Make pass name match DEBUG_TYPE
llvm-svn: 274874
2016-07-08 16:29:11 +00:00
..
AArch64
[MIR] Check that generic virtual registers get a size.
2016-06-08 23:27:46 +00:00
AMDGPU
When printing MIR, output to errs() rather than outs().
2016-02-19 00:18:46 +00:00
ARM
PeepholeOptimizer: Make pass name match DEBUG_TYPE
2016-07-08 16:29:11 +00:00
Generic
PeepholeOptimizer: Make pass name match DEBUG_TYPE
2016-07-08 16:29:11 +00:00
Hexagon
Add test/CodeGen/MIR/Hexagon/lit.local.cfg
2016-05-26 18:35:45 +00:00
Lanai
[lanai] Use peephole optimizer to generate more conditional ALU operations.
2016-07-07 23:36:04 +00:00
Mips
[mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores.
2016-06-16 10:20:59 +00:00
NVPTX
When printing MIR, output to errs() rather than outs().
2016-02-19 00:18:46 +00:00
PowerPC
When printing MIR, output to errs() rather than outs().
2016-02-19 00:18:46 +00:00
X86
[llc] Remove exit-on-error flag from MIR tests (PR27770)
2016-06-09 10:31:05 +00:00
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